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git01.mediatek.com / filogic / uboot / 0f79670975f1c8a79e43451b2e377bade4b2cdae / . / board / ppmc8260 / ppmc8260.c
blob: f0f29b2f687686521e569bfbb2ae3a4fe663547d [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2001
7 * Advent Networks, Inc. <http://www.adventnetworks.com>
8 * Jay Monkman <jtm@smoothsmoothie.com>
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]10 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]11 */
12
13#include <common.h>
14#include <ioports.h>
15#include <mpc8260.h>
16
17/*
18 * I/O Port configuration table
19 *
20 * if conf is 1, then that port pin will be configured at boot time
21 * according to the five values podr/pdir/ppar/psor/pdat for that entry
22 */
23
24const iop_conf_t iop_conf_tab[4][32] = {
25
26
27 /* Port A configuration */
28 { /* conf ppar psor pdir podr pdat */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]29 /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]30 /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */
31 /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */
32 /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */
33 /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */
34 /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */
35 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */
36 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */
37 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */
38 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */
39 /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */
40 /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */
41 /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */
42 /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */
43 /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
44 /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
45 /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
46 /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
47 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
48 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
49 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
50 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
51 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
52 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
53 /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_A1:L1TSYNC */
54 /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* TDN_A1:L1RSYNC */
55 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
56 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
57 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
58 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
59 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
60 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
61 },
62
63 /* Port B configuration */
64 { /* conf ppar psor pdir podr pdat */
65 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
66 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
67 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
68 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
69 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
70 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
71 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
72 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
73 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
74 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
75 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
76 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
77 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
78 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
79 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
80 /* PB16 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_A1:L1CLK0 */
81 /* PB15 */ { 1, 0, 0, 1, 0, 1 }, /* /FETHRST */
82 /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* FETHDIS */
83 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
84 /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_B1:L1CLK0 */
85 /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TXD */
86 /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RXD */
87 /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TSYNC */
88 /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RSYNC */
89 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
90 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
91 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
92 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
93 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
94 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
95 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
96 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
97 },
98
99 /* Port C */
100 { /* conf ppar psor pdir podr pdat */
101 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
102 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
103 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
104 /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* CLK4 */
105 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
106 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
107 /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* CLK7 */
108 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
109 /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* ATMTFCLK */
110 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
111 /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
112 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
113 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
114 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
115 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
116 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
117 /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[0] */
118 /* PC14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[0] */
119 /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[1] */
120 /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[1] */
121 /* PC11 */ { 1, 1, 0, 1, 0, 0 }, /* TDM_D1:L1CLK0 */
122 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
123 /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
124 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
125 /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[2]*/
126 /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[2] */
127 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
128 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
129 /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DACK */
130 /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DONE */
131 /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DREQ */
132 /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DREQ */
133 },
134
135 /* Port D */
136 { /* conf ppar psor pdir podr pdat */
137 /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
138 /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
139 /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[3] */
140 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
141 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
142 /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_C1:L1RSYNC */
143 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
144 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
145 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
146 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
147 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
148 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
149 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
150 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
151 /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
152 /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
153 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
154 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
155 /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TXD */
156 /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RXD */
157 /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TSYNC */
158 /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RSYNC*/
159 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1:TXD */
160 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:RXD */
161 /* PD7 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:SMSYN */
162 /* PD6 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DACK */
163 /* PD5 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DONE */
164 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
165 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
166 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
167 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
168 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
169 }
170};
171
172/* ------------------------------------------------------------------------- */
173
174/*
175 * Check Board Identity:
176 */
177
178int checkboard (void)
179{
180 puts ("Board: Wind River PPMC8260\n");
181 return 0;
182}
183
184/* ------------------------------------------------------------------------- */
185
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]186phys_size_t initdram (int board_type)
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]187{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]188 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]189 volatile memctl8260_t *memctl = &immap->im_memctl;
190 volatile uchar c = 0xff;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]191 volatile uchar *ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE);
192 volatile uchar *ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE);
193 ulong psdmr = CONFIG_SYS_PSDMR;
194 volatile uchar *ramaddr2 = (uchar *) (CONFIG_SYS_SDRAM2_BASE);
195 ulong lsdmr = CONFIG_SYS_LSDMR;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]196 int i;
197
198 /*
199 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
200 *
201 * "At system reset, initialization software must set up the
202 * programmable parameters in the memory controller banks registers
203 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
204 * system software should execute the following initialization sequence
205 * for each SDRAM device.
206 *
207 * 1. Issue a PRECHARGE-ALL-BANKS command
208 * 2. Issue eight CBR REFRESH commands
209 * 3. Issue a MODE-SET command to initialize the mode register
210 *
211 * The initial commands are executed by setting P/LSDMR[OP] and
212 * accessing the SDRAM with a single-byte transaction."
213 *
214 * The appropriate BRx/ORx registers have already been set when we
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]215 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]216 */
217
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]218 memctl->memc_psrt = CONFIG_SYS_PSRT;
219 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]220
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]221#ifndef CONFIG_SYS_RAMBOOT
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]222 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
223 *ramaddr0++ = c;
224 *ramaddr1++ = c;
225
226 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
227 for (i = 0; i < 8; i++) {
228 *ramaddr0++ = c;
229 *ramaddr1++ = c;
230 }
231
232 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]233 ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE + 0x110);
234 ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE + 0x110);
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]235 *ramaddr0 = c;
236 *ramaddr1 = c;
237
238 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
239 *ramaddr0 = c;
240 *ramaddr1 = c;
241
242 memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
243 *ramaddr2++ = c;
244
245 memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR;
246 for (i = 0; i < 8; i++) {
247 *ramaddr2++ = c;
248 }
249
250 memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW;
251 *ramaddr2++ = c;
252
253 memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN;
254 *ramaddr2 = c;
255#endif
256
257 /* return total ram size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]258 return ((CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) * 1024 * 1024);
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]259}
260
261#ifdef CONFIG_MISC_INIT_R
262/* ------------------------------------------------------------------------- */
263int misc_init_r (void)
264{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]265#ifdef CONFIG_SYS_LED_BASE
266 uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1);
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]267 uchar ss;
268 uchar tmp[64];
269 int res;
270
271 if ((ds != 0) && (ds != 0xff)) {
Wolfgang Denk76af2782010-07-24 21:55:43 +0200[diff] [blame]272 res = getenv_f("ethaddr", (char *)tmp, sizeof (tmp));
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]273 if (res > 0) {
274 ss = ((ds >> 4) & 0x0f);
275 ss += ss < 0x0a ? '0' : ('a' - 10);
276 tmp[15] = ss;
277
278 ss = (ds & 0x0f);
279 ss += ss < 0x0a ? '0' : ('a' - 10);
280 tmp[16] = ss;
281
282 tmp[17] = '\0';
Wolfgang Denk7fb52662005-10-13 16:45:02 +0200[diff] [blame]283 setenv ("ethaddr", (char *)tmp);
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]284 /* set the led to show the address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]285 *((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]286 }
287 }
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]288#endif /* CONFIG_SYS_LED_BASE */
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]289 return (0);
290}
291#endif /* CONFIG_MISC_INIT_R */