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git01.mediatek.com / filogic / uboot / 0f33ef24990ed9fcf6d7c29e177902c10f95a41b / . / arch / arm / dts / omap54xx-clocks.dtsi
blob: 42f2c447727dfa045421927afc1e7b360e79867d [file] [log] [blame]
Tero Kristobf4f5972020-06-16 11:03:09 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for OMAP5 clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7&cm_core_aon_clocks {
8 pad_clks_src_ck: pad_clks_src_ck {
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <12000000>;
12 };
13
14 pad_clks_ck: pad_clks_ck@108 {
15 #clock-cells = <0>;
16 compatible = "ti,gate-clock";
17 clocks = <&pad_clks_src_ck>;
18 ti,bit-shift = <8>;
19 reg = <0x0108>;
20 };
21
22 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
26 };
27
28 slimbus_src_clk: slimbus_src_clk {
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <12000000>;
32 };
33
34 slimbus_clk: slimbus_clk@108 {
35 #clock-cells = <0>;
36 compatible = "ti,gate-clock";
37 clocks = <&slimbus_src_clk>;
38 ti,bit-shift = <10>;
39 reg = <0x0108>;
40 };
41
42 sys_32k_ck: sys_32k_ck {
43 #clock-cells = <0>;
44 compatible = "fixed-clock";
45 clock-frequency = <32768>;
46 };
47
48 virt_12000000_ck: virt_12000000_ck {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <12000000>;
52 };
53
54 virt_13000000_ck: virt_13000000_ck {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <13000000>;
58 };
59
60 virt_16800000_ck: virt_16800000_ck {
61 #clock-cells = <0>;
62 compatible = "fixed-clock";
63 clock-frequency = <16800000>;
64 };
65
66 virt_19200000_ck: virt_19200000_ck {
67 #clock-cells = <0>;
68 compatible = "fixed-clock";
69 clock-frequency = <19200000>;
70 };
71
72 virt_26000000_ck: virt_26000000_ck {
73 #clock-cells = <0>;
74 compatible = "fixed-clock";
75 clock-frequency = <26000000>;
76 };
77
78 virt_27000000_ck: virt_27000000_ck {
79 #clock-cells = <0>;
80 compatible = "fixed-clock";
81 clock-frequency = <27000000>;
82 };
83
84 virt_38400000_ck: virt_38400000_ck {
85 #clock-cells = <0>;
86 compatible = "fixed-clock";
87 clock-frequency = <38400000>;
88 };
89
90 xclk60mhsp1_ck: xclk60mhsp1_ck {
91 #clock-cells = <0>;
92 compatible = "fixed-clock";
93 clock-frequency = <60000000>;
94 };
95
96 xclk60mhsp2_ck: xclk60mhsp2_ck {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 clock-frequency = <60000000>;
100 };
101
102 dpll_abe_ck: dpll_abe_ck@1e0 {
103 #clock-cells = <0>;
104 compatible = "ti,omap4-dpll-m4xen-clock";
105 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
106 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
107 };
108
109 dpll_abe_x2_ck: dpll_abe_x2_ck {
110 #clock-cells = <0>;
111 compatible = "ti,omap4-dpll-x2-clock";
112 clocks = <&dpll_abe_ck>;
113 };
114
115 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
116 #clock-cells = <0>;
117 compatible = "ti,divider-clock";
118 clocks = <&dpll_abe_x2_ck>;
119 ti,max-div = <31>;
120 reg = <0x01f0>;
121 ti,index-starts-at-one;
122 };
123
124 abe_24m_fclk: abe_24m_fclk {
125 #clock-cells = <0>;
126 compatible = "fixed-factor-clock";
127 clocks = <&dpll_abe_m2x2_ck>;
128 clock-mult = <1>;
129 clock-div = <8>;
130 };
131
132 abe_clk: abe_clk@108 {
133 #clock-cells = <0>;
134 compatible = "ti,divider-clock";
135 clocks = <&dpll_abe_m2x2_ck>;
136 ti,max-div = <4>;
137 reg = <0x0108>;
138 ti,index-power-of-two;
139 };
140
141 abe_iclk: abe_iclk@528 {
142 #clock-cells = <0>;
143 compatible = "ti,divider-clock";
144 clocks = <&aess_fclk>;
145 ti,bit-shift = <24>;
146 reg = <0x0528>;
147 ti,dividers = <2>, <1>;
148 };
149
150 abe_lp_clk_div: abe_lp_clk_div {
151 #clock-cells = <0>;
152 compatible = "fixed-factor-clock";
153 clocks = <&dpll_abe_m2x2_ck>;
154 clock-mult = <1>;
155 clock-div = <16>;
156 };
157
158 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
159 #clock-cells = <0>;
160 compatible = "ti,divider-clock";
161 clocks = <&dpll_abe_x2_ck>;
162 ti,max-div = <31>;
163 reg = <0x01f4>;
164 ti,index-starts-at-one;
165 };
166
167 dpll_core_byp_mux: dpll_core_byp_mux@12c {
168 #clock-cells = <0>;
169 compatible = "ti,mux-clock";
170 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
171 ti,bit-shift = <23>;
172 reg = <0x012c>;
173 };
174
175 dpll_core_ck: dpll_core_ck@120 {
176 #clock-cells = <0>;
177 compatible = "ti,omap4-dpll-core-clock";
178 clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
179 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
180 };
181
182 dpll_core_x2_ck: dpll_core_x2_ck {
183 #clock-cells = <0>;
184 compatible = "ti,omap4-dpll-x2-clock";
185 clocks = <&dpll_core_ck>;
186 };
187
188 dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
189 #clock-cells = <0>;
190 compatible = "ti,divider-clock";
191 clocks = <&dpll_core_x2_ck>;
192 ti,max-div = <63>;
193 reg = <0x0150>;
194 ti,index-starts-at-one;
195 };
196
197 c2c_fclk: c2c_fclk {
198 #clock-cells = <0>;
199 compatible = "fixed-factor-clock";
200 clocks = <&dpll_core_h21x2_ck>;
201 clock-mult = <1>;
202 clock-div = <1>;
203 };
204
205 c2c_iclk: c2c_iclk {
206 #clock-cells = <0>;
207 compatible = "fixed-factor-clock";
208 clocks = <&c2c_fclk>;
209 clock-mult = <1>;
210 clock-div = <2>;
211 };
212
213 dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
214 #clock-cells = <0>;
215 compatible = "ti,divider-clock";
216 clocks = <&dpll_core_x2_ck>;
217 ti,max-div = <63>;
218 reg = <0x0138>;
219 ti,index-starts-at-one;
220 };
221
222 dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
223 #clock-cells = <0>;
224 compatible = "ti,divider-clock";
225 clocks = <&dpll_core_x2_ck>;
226 ti,max-div = <63>;
227 reg = <0x013c>;
228 ti,index-starts-at-one;
229 };
230
231 dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
232 #clock-cells = <0>;
233 compatible = "ti,divider-clock";
234 clocks = <&dpll_core_x2_ck>;
235 ti,max-div = <63>;
236 reg = <0x0140>;
237 ti,index-starts-at-one;
238 };
239
240 dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
241 #clock-cells = <0>;
242 compatible = "ti,divider-clock";
243 clocks = <&dpll_core_x2_ck>;
244 ti,max-div = <63>;
245 reg = <0x0144>;
246 ti,index-starts-at-one;
247 };
248
249 dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
250 #clock-cells = <0>;
251 compatible = "ti,divider-clock";
252 clocks = <&dpll_core_x2_ck>;
253 ti,max-div = <63>;
254 reg = <0x0154>;
255 ti,index-starts-at-one;
256 };
257
258 dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
259 #clock-cells = <0>;
260 compatible = "ti,divider-clock";
261 clocks = <&dpll_core_x2_ck>;
262 ti,max-div = <63>;
263 reg = <0x0158>;
264 ti,index-starts-at-one;
265 };
266
267 dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
268 #clock-cells = <0>;
269 compatible = "ti,divider-clock";
270 clocks = <&dpll_core_x2_ck>;
271 ti,max-div = <63>;
272 reg = <0x015c>;
273 ti,index-starts-at-one;
274 };
275
276 dpll_core_m2_ck: dpll_core_m2_ck@130 {
277 #clock-cells = <0>;
278 compatible = "ti,divider-clock";
279 clocks = <&dpll_core_ck>;
280 ti,max-div = <31>;
281 reg = <0x0130>;
282 ti,index-starts-at-one;
283 };
284
285 dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
286 #clock-cells = <0>;
287 compatible = "ti,divider-clock";
288 clocks = <&dpll_core_x2_ck>;
289 ti,max-div = <31>;
290 reg = <0x0134>;
291 ti,index-starts-at-one;
292 };
293
294 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
295 #clock-cells = <0>;
296 compatible = "fixed-factor-clock";
297 clocks = <&dpll_core_h12x2_ck>;
298 clock-mult = <1>;
299 clock-div = <1>;
300 };
301
302 dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
303 #clock-cells = <0>;
304 compatible = "ti,mux-clock";
305 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
306 ti,bit-shift = <23>;
307 reg = <0x01ac>;
308 };
309
310 dpll_iva_ck: dpll_iva_ck@1a0 {
311 #clock-cells = <0>;
312 compatible = "ti,omap4-dpll-clock";
313 clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
314 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
315 assigned-clocks = <&dpll_iva_ck>;
316 assigned-clock-rates = <1165000000>;
317 };
318
319 dpll_iva_x2_ck: dpll_iva_x2_ck {
320 #clock-cells = <0>;
321 compatible = "ti,omap4-dpll-x2-clock";
322 clocks = <&dpll_iva_ck>;
323 };
324
325 dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
326 #clock-cells = <0>;
327 compatible = "ti,divider-clock";
328 clocks = <&dpll_iva_x2_ck>;
329 ti,max-div = <63>;
330 reg = <0x01b8>;
331 ti,index-starts-at-one;
332 assigned-clocks = <&dpll_iva_h11x2_ck>;
333 assigned-clock-rates = <465920000>;
334 };
335
336 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
337 #clock-cells = <0>;
338 compatible = "ti,divider-clock";
339 clocks = <&dpll_iva_x2_ck>;
340 ti,max-div = <63>;
341 reg = <0x01bc>;
342 ti,index-starts-at-one;
343 assigned-clocks = <&dpll_iva_h12x2_ck>;
344 assigned-clock-rates = <388300000>;
345 };
346
347 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
348 #clock-cells = <0>;
349 compatible = "fixed-factor-clock";
350 clocks = <&dpll_core_h12x2_ck>;
351 clock-mult = <1>;
352 clock-div = <1>;
353 };
354
355 dpll_mpu_ck: dpll_mpu_ck@160 {
356 #clock-cells = <0>;
357 compatible = "ti,omap5-mpu-dpll-clock";
358 clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
359 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
360 };
361
362 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
363 #clock-cells = <0>;
364 compatible = "ti,divider-clock";
365 clocks = <&dpll_mpu_ck>;
366 ti,max-div = <31>;
367 reg = <0x0170>;
368 ti,index-starts-at-one;
369 };
370
371 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
372 #clock-cells = <0>;
373 compatible = "fixed-factor-clock";
374 clocks = <&dpll_abe_m3x2_ck>;
375 clock-mult = <1>;
376 clock-div = <2>;
377 };
378
379 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
380 #clock-cells = <0>;
381 compatible = "fixed-factor-clock";
382 clocks = <&dpll_abe_m3x2_ck>;
383 clock-mult = <1>;
384 clock-div = <3>;
385 };
386
387 l3_iclk_div: l3_iclk_div@100 {
388 #clock-cells = <0>;
389 compatible = "ti,divider-clock";
390 ti,max-div = <2>;
391 ti,bit-shift = <4>;
392 reg = <0x100>;
393 clocks = <&dpll_core_h12x2_ck>;
394 ti,index-power-of-two;
395 };
396
397 gpu_l3_iclk: gpu_l3_iclk {
398 #clock-cells = <0>;
399 compatible = "fixed-factor-clock";
400 clocks = <&l3_iclk_div>;
401 clock-mult = <1>;
402 clock-div = <1>;
403 };
404
405 l4_root_clk_div: l4_root_clk_div@100 {
406 #clock-cells = <0>;
407 compatible = "ti,divider-clock";
408 ti,max-div = <2>;
409 ti,bit-shift = <8>;
410 reg = <0x100>;
411 clocks = <&l3_iclk_div>;
412 ti,index-power-of-two;
413 };
414
415 slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
416 #clock-cells = <0>;
417 compatible = "ti,gate-clock";
418 clocks = <&slimbus_clk>;
419 ti,bit-shift = <11>;
420 reg = <0x0560>;
421 };
422
423 aess_fclk: aess_fclk@528 {
424 #clock-cells = <0>;
425 compatible = "ti,divider-clock";
426 clocks = <&abe_clk>;
427 ti,bit-shift = <24>;
428 ti,max-div = <2>;
429 reg = <0x0528>;
430 };
431
432 mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
433 #clock-cells = <0>;
434 compatible = "ti,mux-clock";
435 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
436 ti,bit-shift = <26>;
437 reg = <0x0540>;
438 };
439
440 mcasp_gfclk: mcasp_gfclk@540 {
441 #clock-cells = <0>;
442 compatible = "ti,mux-clock";
443 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
444 ti,bit-shift = <24>;
445 reg = <0x0540>;
446 };
447
448 dummy_ck: dummy_ck {
449 #clock-cells = <0>;
450 compatible = "fixed-clock";
451 clock-frequency = <0>;
452 };
453};
454&prm_clocks {
455 sys_clkin: sys_clkin@110 {
456 #clock-cells = <0>;
457 compatible = "ti,mux-clock";
458 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
459 reg = <0x0110>;
460 ti,index-starts-at-one;
461 };
462
463 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
464 #clock-cells = <0>;
465 compatible = "ti,mux-clock";
466 clocks = <&sys_clkin>, <&sys_32k_ck>;
467 reg = <0x0108>;
468 };
469
470 abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
471 #clock-cells = <0>;
472 compatible = "ti,mux-clock";
473 clocks = <&sys_clkin>, <&sys_32k_ck>;
474 reg = <0x010c>;
475 };
476
477 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
478 #clock-cells = <0>;
479 compatible = "fixed-factor-clock";
480 clocks = <&sys_clkin>;
481 clock-mult = <1>;
482 clock-div = <2>;
483 };
484
485 dss_syc_gfclk_div: dss_syc_gfclk_div {
486 #clock-cells = <0>;
487 compatible = "fixed-factor-clock";
488 clocks = <&sys_clkin>;
489 clock-mult = <1>;
490 clock-div = <1>;
491 };
492
493 wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
494 #clock-cells = <0>;
495 compatible = "ti,mux-clock";
496 clocks = <&sys_clkin>, <&abe_lp_clk_div>;
497 reg = <0x0108>;
498 };
499
500 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
501 #clock-cells = <0>;
502 compatible = "fixed-factor-clock";
503 clocks = <&wkupaon_iclk_mux>;
504 clock-mult = <1>;
505 clock-div = <1>;
506 };
507};
508
509&cm_core_clocks {
510
511 dpll_per_byp_mux: dpll_per_byp_mux@14c {
512 #clock-cells = <0>;
513 compatible = "ti,mux-clock";
514 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
515 ti,bit-shift = <23>;
516 reg = <0x014c>;
517 };
518
519 dpll_per_ck: dpll_per_ck@140 {
520 #clock-cells = <0>;
521 compatible = "ti,omap4-dpll-clock";
522 clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
523 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
524 };
525
526 dpll_per_x2_ck: dpll_per_x2_ck {
527 #clock-cells = <0>;
528 compatible = "ti,omap4-dpll-x2-clock";
529 clocks = <&dpll_per_ck>;
530 };
531
532 dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
533 #clock-cells = <0>;
534 compatible = "ti,divider-clock";
535 clocks = <&dpll_per_x2_ck>;
536 ti,max-div = <63>;
537 reg = <0x0158>;
538 ti,index-starts-at-one;
539 };
540
541 dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
542 #clock-cells = <0>;
543 compatible = "ti,divider-clock";
544 clocks = <&dpll_per_x2_ck>;
545 ti,max-div = <63>;
546 reg = <0x015c>;
547 ti,index-starts-at-one;
548 };
549
550 dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
551 #clock-cells = <0>;
552 compatible = "ti,divider-clock";
553 clocks = <&dpll_per_x2_ck>;
554 ti,max-div = <63>;
555 reg = <0x0164>;
556 ti,index-starts-at-one;
557 };
558
559 dpll_per_m2_ck: dpll_per_m2_ck@150 {
560 #clock-cells = <0>;
561 compatible = "ti,divider-clock";
562 clocks = <&dpll_per_ck>;
563 ti,max-div = <31>;
564 reg = <0x0150>;
565 ti,index-starts-at-one;
566 };
567
568 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
569 #clock-cells = <0>;
570 compatible = "ti,divider-clock";
571 clocks = <&dpll_per_x2_ck>;
572 ti,max-div = <31>;
573 reg = <0x0150>;
574 ti,index-starts-at-one;
575 };
576
577 dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
578 #clock-cells = <0>;
579 compatible = "ti,divider-clock";
580 clocks = <&dpll_per_x2_ck>;
581 ti,max-div = <31>;
582 reg = <0x0154>;
583 ti,index-starts-at-one;
584 };
585
586 dpll_unipro1_ck: dpll_unipro1_ck@200 {
587 #clock-cells = <0>;
588 compatible = "ti,omap4-dpll-clock";
589 clocks = <&sys_clkin>, <&sys_clkin>;
590 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
591 };
592
593 dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
594 #clock-cells = <0>;
595 compatible = "fixed-factor-clock";
596 clocks = <&dpll_unipro1_ck>;
597 clock-mult = <1>;
598 clock-div = <1>;
599 };
600
601 dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
602 #clock-cells = <0>;
603 compatible = "ti,divider-clock";
604 clocks = <&dpll_unipro1_ck>;
605 ti,max-div = <127>;
606 reg = <0x0210>;
607 ti,index-starts-at-one;
608 };
609
610 dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
611 #clock-cells = <0>;
612 compatible = "ti,omap4-dpll-clock";
613 clocks = <&sys_clkin>, <&sys_clkin>;
614 reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
615 };
616
617 dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
618 #clock-cells = <0>;
619 compatible = "fixed-factor-clock";
620 clocks = <&dpll_unipro2_ck>;
621 clock-mult = <1>;
622 clock-div = <1>;
623 };
624
625 dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
626 #clock-cells = <0>;
627 compatible = "ti,divider-clock";
628 clocks = <&dpll_unipro2_ck>;
629 ti,max-div = <127>;
630 reg = <0x01d0>;
631 ti,index-starts-at-one;
632 };
633
634 dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
635 #clock-cells = <0>;
636 compatible = "ti,mux-clock";
637 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
638 ti,bit-shift = <23>;
639 reg = <0x018c>;
640 };
641
642 dpll_usb_ck: dpll_usb_ck@180 {
643 #clock-cells = <0>;
644 compatible = "ti,omap4-dpll-j-type-clock";
645 clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
646 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
647 };
648
649 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
650 #clock-cells = <0>;
651 compatible = "fixed-factor-clock";
652 clocks = <&dpll_usb_ck>;
653 clock-mult = <1>;
654 clock-div = <1>;
655 };
656
657 dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
658 #clock-cells = <0>;
659 compatible = "ti,divider-clock";
660 clocks = <&dpll_usb_ck>;
661 ti,max-div = <127>;
662 reg = <0x0190>;
663 ti,index-starts-at-one;
664 };
665
666 func_128m_clk: func_128m_clk {
667 #clock-cells = <0>;
668 compatible = "fixed-factor-clock";
669 clocks = <&dpll_per_h11x2_ck>;
670 clock-mult = <1>;
671 clock-div = <2>;
672 };
673
674 func_12m_fclk: func_12m_fclk {
675 #clock-cells = <0>;
676 compatible = "fixed-factor-clock";
677 clocks = <&dpll_per_m2x2_ck>;
678 clock-mult = <1>;
679 clock-div = <16>;
680 };
681
682 func_24m_clk: func_24m_clk {
683 #clock-cells = <0>;
684 compatible = "fixed-factor-clock";
685 clocks = <&dpll_per_m2_ck>;
686 clock-mult = <1>;
687 clock-div = <4>;
688 };
689
690 func_48m_fclk: func_48m_fclk {
691 #clock-cells = <0>;
692 compatible = "fixed-factor-clock";
693 clocks = <&dpll_per_m2x2_ck>;
694 clock-mult = <1>;
695 clock-div = <4>;
696 };
697
698 func_96m_fclk: func_96m_fclk {
699 #clock-cells = <0>;
700 compatible = "fixed-factor-clock";
701 clocks = <&dpll_per_m2x2_ck>;
702 clock-mult = <1>;
703 clock-div = <2>;
704 };
705
706 l3init_60m_fclk: l3init_60m_fclk@104 {
707 #clock-cells = <0>;
708 compatible = "ti,divider-clock";
709 clocks = <&dpll_usb_m2_ck>;
710 reg = <0x0104>;
711 ti,dividers = <1>, <8>;
712 };
713
714 iss_ctrlclk: iss_ctrlclk@1320 {
715 #clock-cells = <0>;
716 compatible = "ti,gate-clock";
717 clocks = <&func_96m_fclk>;
718 ti,bit-shift = <8>;
719 reg = <0x1320>;
720 };
721
722 lli_txphy_clk: lli_txphy_clk@f20 {
723 #clock-cells = <0>;
724 compatible = "ti,gate-clock";
725 clocks = <&dpll_unipro1_clkdcoldo>;
726 ti,bit-shift = <8>;
727 reg = <0x0f20>;
728 };
729
730 lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
731 #clock-cells = <0>;
732 compatible = "ti,gate-clock";
733 clocks = <&dpll_unipro1_m2_ck>;
734 ti,bit-shift = <9>;
735 reg = <0x0f20>;
736 };
737
738 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
739 #clock-cells = <0>;
740 compatible = "ti,gate-clock";
741 clocks = <&sys_32k_ck>;
742 ti,bit-shift = <8>;
743 reg = <0x0640>;
744 };
745
746 fdif_fclk: fdif_fclk@1328 {
747 #clock-cells = <0>;
748 compatible = "ti,divider-clock";
749 clocks = <&dpll_per_h11x2_ck>;
750 ti,bit-shift = <24>;
751 ti,max-div = <2>;
752 reg = <0x1328>;
753 };
754
755 gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
756 #clock-cells = <0>;
757 compatible = "ti,mux-clock";
758 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
759 ti,bit-shift = <24>;
760 reg = <0x1520>;
761 };
762
763 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
764 #clock-cells = <0>;
765 compatible = "ti,mux-clock";
766 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
767 ti,bit-shift = <25>;
768 reg = <0x1520>;
769 };
770
771 hsi_fclk: hsi_fclk@1638 {
772 #clock-cells = <0>;
773 compatible = "ti,divider-clock";
774 clocks = <&dpll_per_m2x2_ck>;
775 ti,bit-shift = <24>;
776 ti,max-div = <2>;
777 reg = <0x1638>;
778 };
779};
780
781&cm_core_clockdomains {
782 l3init_clkdm: l3init_clkdm {
783 compatible = "ti,clockdomain";
784 clocks = <&dpll_usb_ck>;
785 };
786};
787
788&scrm_clocks {
789 auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
790 #clock-cells = <0>;
791 compatible = "ti,composite-no-wait-gate-clock";
792 clocks = <&dpll_core_m3x2_ck>;
793 ti,bit-shift = <8>;
794 reg = <0x0310>;
795 };
796
797 auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
798 #clock-cells = <0>;
799 compatible = "ti,composite-mux-clock";
800 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
801 ti,bit-shift = <1>;
802 reg = <0x0310>;
803 };
804
805 auxclk0_src_ck: auxclk0_src_ck {
806 #clock-cells = <0>;
807 compatible = "ti,composite-clock";
808 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
809 };
810
811 auxclk0_ck: auxclk0_ck@310 {
812 #clock-cells = <0>;
813 compatible = "ti,divider-clock";
814 clocks = <&auxclk0_src_ck>;
815 ti,bit-shift = <16>;
816 ti,max-div = <16>;
817 reg = <0x0310>;
818 };
819
820 auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
821 #clock-cells = <0>;
822 compatible = "ti,composite-no-wait-gate-clock";
823 clocks = <&dpll_core_m3x2_ck>;
824 ti,bit-shift = <8>;
825 reg = <0x0314>;
826 };
827
828 auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
829 #clock-cells = <0>;
830 compatible = "ti,composite-mux-clock";
831 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
832 ti,bit-shift = <1>;
833 reg = <0x0314>;
834 };
835
836 auxclk1_src_ck: auxclk1_src_ck {
837 #clock-cells = <0>;
838 compatible = "ti,composite-clock";
839 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
840 };
841
842 auxclk1_ck: auxclk1_ck@314 {
843 #clock-cells = <0>;
844 compatible = "ti,divider-clock";
845 clocks = <&auxclk1_src_ck>;
846 ti,bit-shift = <16>;
847 ti,max-div = <16>;
848 reg = <0x0314>;
849 };
850
851 auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
852 #clock-cells = <0>;
853 compatible = "ti,composite-no-wait-gate-clock";
854 clocks = <&dpll_core_m3x2_ck>;
855 ti,bit-shift = <8>;
856 reg = <0x0318>;
857 };
858
859 auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
860 #clock-cells = <0>;
861 compatible = "ti,composite-mux-clock";
862 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
863 ti,bit-shift = <1>;
864 reg = <0x0318>;
865 };
866
867 auxclk2_src_ck: auxclk2_src_ck {
868 #clock-cells = <0>;
869 compatible = "ti,composite-clock";
870 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
871 };
872
873 auxclk2_ck: auxclk2_ck@318 {
874 #clock-cells = <0>;
875 compatible = "ti,divider-clock";
876 clocks = <&auxclk2_src_ck>;
877 ti,bit-shift = <16>;
878 ti,max-div = <16>;
879 reg = <0x0318>;
880 };
881
882 auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
883 #clock-cells = <0>;
884 compatible = "ti,composite-no-wait-gate-clock";
885 clocks = <&dpll_core_m3x2_ck>;
886 ti,bit-shift = <8>;
887 reg = <0x031c>;
888 };
889
890 auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
891 #clock-cells = <0>;
892 compatible = "ti,composite-mux-clock";
893 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
894 ti,bit-shift = <1>;
895 reg = <0x031c>;
896 };
897
898 auxclk3_src_ck: auxclk3_src_ck {
899 #clock-cells = <0>;
900 compatible = "ti,composite-clock";
901 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
902 };
903
904 auxclk3_ck: auxclk3_ck@31c {
905 #clock-cells = <0>;
906 compatible = "ti,divider-clock";
907 clocks = <&auxclk3_src_ck>;
908 ti,bit-shift = <16>;
909 ti,max-div = <16>;
910 reg = <0x031c>;
911 };
912
913 auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
914 #clock-cells = <0>;
915 compatible = "ti,composite-no-wait-gate-clock";
916 clocks = <&dpll_core_m3x2_ck>;
917 ti,bit-shift = <8>;
918 reg = <0x0320>;
919 };
920
921 auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
922 #clock-cells = <0>;
923 compatible = "ti,composite-mux-clock";
924 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
925 ti,bit-shift = <1>;
926 reg = <0x0320>;
927 };
928
929 auxclk4_src_ck: auxclk4_src_ck {
930 #clock-cells = <0>;
931 compatible = "ti,composite-clock";
932 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
933 };
934
935 auxclk4_ck: auxclk4_ck@320 {
936 #clock-cells = <0>;
937 compatible = "ti,divider-clock";
938 clocks = <&auxclk4_src_ck>;
939 ti,bit-shift = <16>;
940 ti,max-div = <16>;
941 reg = <0x0320>;
942 };
943
944 auxclkreq0_ck: auxclkreq0_ck@210 {
945 #clock-cells = <0>;
946 compatible = "ti,mux-clock";
947 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
948 ti,bit-shift = <2>;
949 reg = <0x0210>;
950 };
951
952 auxclkreq1_ck: auxclkreq1_ck@214 {
953 #clock-cells = <0>;
954 compatible = "ti,mux-clock";
955 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
956 ti,bit-shift = <2>;
957 reg = <0x0214>;
958 };
959
960 auxclkreq2_ck: auxclkreq2_ck@218 {
961 #clock-cells = <0>;
962 compatible = "ti,mux-clock";
963 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
964 ti,bit-shift = <2>;
965 reg = <0x0218>;
966 };
967
968 auxclkreq3_ck: auxclkreq3_ck@21c {
969 #clock-cells = <0>;
970 compatible = "ti,mux-clock";
971 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
972 ti,bit-shift = <2>;
973 reg = <0x021c>;
974 };
975};
976
977&cm_core_aon {
978 mpu_cm: mpu_cm@300 {
979 compatible = "ti,omap4-cm";
980 reg = <0x300 0x100>;
981 #address-cells = <1>;
982 #size-cells = <1>;
983 ranges = <0 0x300 0x100>;
984
985 mpu_clkctrl: clk@20 {
986 compatible = "ti,clkctrl";
987 reg = <0x20 0x4>;
988 #clock-cells = <2>;
989 };
990 };
991
992 dsp_cm: dsp_cm@400 {
993 compatible = "ti,omap4-cm";
994 reg = <0x400 0x100>;
995 #address-cells = <1>;
996 #size-cells = <1>;
997 ranges = <0 0x400 0x100>;
998
999 dsp_clkctrl: clk@20 {
1000 compatible = "ti,clkctrl";
1001 reg = <0x20 0x4>;
1002 #clock-cells = <2>;
1003 };
1004 };
1005
1006 abe_cm: abe_cm@500 {
1007 compatible = "ti,omap4-cm";
1008 reg = <0x500 0x100>;
1009 #address-cells = <1>;
1010 #size-cells = <1>;
1011 ranges = <0 0x500 0x100>;
1012
1013 abe_clkctrl: clk@20 {
1014 compatible = "ti,clkctrl";
1015 reg = <0x20 0x64>;
1016 #clock-cells = <2>;
1017 };
1018 };
1019
1020};
1021
1022&cm_core {
1023 l3main1_cm: l3main1_cm@700 {
1024 compatible = "ti,omap4-cm";
1025 reg = <0x700 0x100>;
1026 #address-cells = <1>;
1027 #size-cells = <1>;
1028 ranges = <0 0x700 0x100>;
1029
1030 l3main1_clkctrl: clk@20 {
1031 compatible = "ti,clkctrl";
1032 reg = <0x20 0x4>;
1033 #clock-cells = <2>;
1034 };
1035 };
1036
1037 l3main2_cm: l3main2_cm@800 {
1038 compatible = "ti,omap4-cm";
1039 reg = <0x800 0x100>;
1040 #address-cells = <1>;
1041 #size-cells = <1>;
1042 ranges = <0 0x800 0x100>;
1043
1044 l3main2_clkctrl: clk@20 {
1045 compatible = "ti,clkctrl";
1046 reg = <0x20 0x4>;
1047 #clock-cells = <2>;
1048 };
1049 };
1050
1051 ipu_cm: ipu_cm@900 {
1052 compatible = "ti,omap4-cm";
1053 reg = <0x900 0x100>;
1054 #address-cells = <1>;
1055 #size-cells = <1>;
1056 ranges = <0 0x900 0x100>;
1057
1058 ipu_clkctrl: clk@20 {
1059 compatible = "ti,clkctrl";
1060 reg = <0x20 0x4>;
1061 #clock-cells = <2>;
1062 };
1063 };
1064
1065 dma_cm: dma_cm@a00 {
1066 compatible = "ti,omap4-cm";
1067 reg = <0xa00 0x100>;
1068 #address-cells = <1>;
1069 #size-cells = <1>;
1070 ranges = <0 0xa00 0x100>;
1071
1072 dma_clkctrl: clk@20 {
1073 compatible = "ti,clkctrl";
1074 reg = <0x20 0x4>;
1075 #clock-cells = <2>;
1076 };
1077 };
1078
1079 emif_cm: emif_cm@b00 {
1080 compatible = "ti,omap4-cm";
1081 reg = <0xb00 0x100>;
1082 #address-cells = <1>;
1083 #size-cells = <1>;
1084 ranges = <0 0xb00 0x100>;
1085
1086 emif_clkctrl: clk@20 {
1087 compatible = "ti,clkctrl";
1088 reg = <0x20 0x1c>;
1089 #clock-cells = <2>;
1090 };
1091 };
1092
1093 l4cfg_cm: l4cfg_cm@d00 {
1094 compatible = "ti,omap4-cm";
1095 reg = <0xd00 0x100>;
1096 #address-cells = <1>;
1097 #size-cells = <1>;
1098 ranges = <0 0xd00 0x100>;
1099
1100 l4cfg_clkctrl: clk@20 {
1101 compatible = "ti,clkctrl";
1102 reg = <0x20 0x14>;
1103 #clock-cells = <2>;
1104 };
1105 };
1106
1107 l3instr_cm: l3instr_cm@e00 {
1108 compatible = "ti,omap4-cm";
1109 reg = <0xe00 0x100>;
1110 #address-cells = <1>;
1111 #size-cells = <1>;
1112 ranges = <0 0xe00 0x100>;
1113
1114 l3instr_clkctrl: clk@20 {
1115 compatible = "ti,clkctrl";
1116 reg = <0x20 0xc>;
1117 #clock-cells = <2>;
1118 };
1119 };
1120
1121 l4per_cm: l4per_cm@1000 {
1122 compatible = "ti,omap4-cm";
1123 reg = <0x1000 0x200>;
1124 #address-cells = <1>;
1125 #size-cells = <1>;
1126 ranges = <0 0x1000 0x200>;
1127
1128 l4per_clkctrl: clock@20 {
1129 compatible = "ti,clkctrl-l4per", "ti,clkctrl";
1130 reg = <0x20 0x15c>;
1131 #clock-cells = <2>;
1132 };
1133
1134 l4sec_clkctrl: clock@1a0 {
1135 compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
1136 reg = <0x1a0 0x3c>;
1137 #clock-cells = <2>;
1138 };
1139 };
1140
1141 dss_cm: dss_cm@1400 {
1142 compatible = "ti,omap4-cm";
1143 reg = <0x1400 0x100>;
1144 #address-cells = <1>;
1145 #size-cells = <1>;
1146 ranges = <0 0x1400 0x100>;
1147
1148 dss_clkctrl: clk@20 {
1149 compatible = "ti,clkctrl";
1150 reg = <0x20 0x4>;
1151 #clock-cells = <2>;
1152 };
1153 };
1154
1155 gpu_cm: gpu_cm@1500 {
1156 compatible = "ti,omap4-cm";
1157 reg = <0x1500 0x100>;
1158 #address-cells = <1>;
1159 #size-cells = <1>;
1160 ranges = <0 0x1500 0x100>;
1161
1162 gpu_clkctrl: clk@20 {
1163 compatible = "ti,clkctrl";
1164 reg = <0x20 0x4>;
1165 #clock-cells = <2>;
1166 };
1167 };
1168
1169 l3init_cm: l3init_cm@1600 {
1170 compatible = "ti,omap4-cm";
1171 reg = <0x1600 0x100>;
1172 #address-cells = <1>;
1173 #size-cells = <1>;
1174 ranges = <0 0x1600 0x100>;
1175
1176 l3init_clkctrl: clk@20 {
1177 compatible = "ti,clkctrl";
1178 reg = <0x20 0xd4>;
1179 #clock-cells = <2>;
1180 };
1181 };
1182};
1183
1184&prm {
1185 wkupaon_cm: wkupaon_cm@1900 {
1186 compatible = "ti,omap4-cm";
1187 reg = <0x1900 0x100>;
1188 #address-cells = <1>;
1189 #size-cells = <1>;
1190 ranges = <0 0x1900 0x100>;
1191
1192 wkupaon_clkctrl: clk@20 {
1193 compatible = "ti,clkctrl";
1194 reg = <0x20 0x5c>;
1195 #clock-cells = <2>;
1196 };
1197 };
1198};
1199
1200&scm_wkup_pad_conf_clocks {
1201 fref_xtal_ck: fref_xtal_ck {
1202 #clock-cells = <0>;
1203 compatible = "ti,gate-clock";
1204 clocks = <&sys_clkin>;
1205 ti,bit-shift = <28>;
1206 reg = <0x14>;
1207 };
1208};