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git01.mediatek.com / filogic / uboot / 0f30f0cd4a8f3c49a29a8af7391f6fdcfb630b3d / . / arch / arm / dts / k3-am625-sk-u-boot.dtsi
blob: 249155733a24a03f0551a887d3006ab3d2be9039 [file] [log] [blame]
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common AM625 SK dts file for SPLs
4 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
7/ {
8 chosen {
9 stdout-path = "serial2:115200n8";
10 tick-timer = &timer1;
11 };
12
13 aliases {
14 mmc1 = &sdhci1;
15 };
Georgi Vlaeve9c68bf2022-06-14 17:45:31 +0300[diff] [blame]16
17 memory@80000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Georgi Vlaeve9c68bf2022-06-14 17:45:31 +0300[diff] [blame]19 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]20};
21
22&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]23 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]24
25 timer1: timer@2400000 {
26 compatible = "ti,omap5430-timer";
27 reg = <0x00 0x2400000 0x00 0x80>;
28 ti,timer-alwon;
29 clock-frequency = <25000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]31 };
32};
33
34&dmss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]36};
37
38&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]40};
41
42&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]44};
45
46&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]48};
49
50&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]52};
53
54&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]56};
57
58&wkup_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]60};
61
62&chipid {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]64};
65
66&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]68};
69
70&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]72};
73
74&main_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]76};
77
78&main_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]80};
81
82&cbass_mcu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]84};
85
86&cbass_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]88};
89
90&mcu_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]92};
93
94&wkup_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]96};
97
98&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]100};
101
102&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530[diff] [blame]104};
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]105
106&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]108};
109
110&ospi0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]112};
113
114&ospi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]116
117 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]119
120 partitions {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]122
123 partition@3fc0000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Dhruva Gole0f33ef22022-10-27 20:23:10 +0530[diff] [blame]125 };
126 };
127 };
128};
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]129
130&cpsw3g {
131 reg = <0x0 0x8000000 0x0 0x200000>,
132 <0x0 0x43000200 0x0 0x8>;
133 reg-names = "cpsw_nuss", "mac_efuse";
134 /delete-property/ ranges;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]135 bootph-pre-ram;
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]136
137 cpsw-phy-sel@04044 {
138 compatible = "ti,am64-phy-gmii-sel";
139 reg = <0x0 0x00104044 0x0 0x8>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]140 bootph-pre-ram;
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]141 };
142};
143
144&cpsw_port1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]145 bootph-pre-ram;
Sjoerd Simons7fb6d4a2022-12-20 16:21:45 +0100[diff] [blame]146};
147
148&cpsw_port2 {
149 status = "disabled";
150};