| Anton Staaf | 7dbd92f | 2011-10-17 16:46:09 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
| Anton Staaf | 7dbd92f | 2011-10-17 16:46:09 -0700 | [diff] [blame] | 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Anton Staaf | 7dbd92f | 2011-10-17 16:46:09 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __AVR32_CACHE_H__ |
| 8 | #define __AVR32_CACHE_H__ |
| 9 | |
| 10 | /* |
| 11 | * Since the AVR32 architecture has a queryable cacheline size with a maximum |
| 12 | * value of 256 we set the DMA buffer alignemnt requirement to this maximum |
| 13 | * value. The board config can override this if it knows that the cacheline |
| 14 | * size is a smaller value. AVR32 boards use the CONFIG_SYS_DCACHE_LINESZ |
| 15 | * macro to specify cache line size, so if it is set we use it instead. |
| 16 | */ |
| 17 | #ifdef CONFIG_SYS_CACHELINE_SIZE |
| 18 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
| 19 | #elif defined(CONFIG_SYS_DCACHE_LINESZ) |
| 20 | #define ARCH_DMA_MINALIGN CONFIG_SYS_DCACHE_LINESZ |
| 21 | #else |
| 22 | #define ARCH_DMA_MINALIGN 256 |
| 23 | #endif |
| 24 | |
| 25 | #endif /* __AVR32_CACHE_H__ */ |