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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simekaf482d52012-09-28 09:56:37 +00002/*
3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
Michal Simek98d0f1f2018-01-17 07:37:47 +01004 * (C) Copyright 2013 - 2018 Xilinx, Inc.
Michal Simekaf482d52012-09-28 09:56:37 +00005 */
6
7#include <common.h>
Michal Simek309ef802018-02-21 17:04:28 +01008#include <dm/uclass.h>
Michal Simek65ef52f2014-02-24 11:16:32 +01009#include <fdtdec.h>
Michal Simek0f796702014-04-25 13:51:17 +020010#include <fpga.h>
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053011#include <malloc.h>
Michal Simek0f796702014-04-25 13:51:17 +020012#include <mmc.h>
Michal Simekc07b2252018-06-08 13:45:14 +020013#include <watchdog.h>
Michal Simek309ef802018-02-21 17:04:28 +010014#include <wdt.h>
Michal Simek15d654c2013-04-22 15:43:02 +020015#include <zynqpl.h>
Michal Simek242192b2013-04-12 16:33:08 +020016#include <asm/arch/hardware.h>
17#include <asm/arch/sys_proto.h>
Michal Simekaf482d52012-09-28 09:56:37 +000018
19DECLARE_GLOBAL_DATA_PTR;
20
Michal Simek309ef802018-02-21 17:04:28 +010021#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
22int board_early_init_f(void)
23{
Michal Simek309ef802018-02-21 17:04:28 +010024 return 0;
25}
26#endif
27
Michal Simekaf482d52012-09-28 09:56:37 +000028int board_init(void)
29{
Michal Simekaf482d52012-09-28 09:56:37 +000030 return 0;
31}
32
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053033int board_late_init(void)
34{
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053035 int env_targets_len = 0;
36 const char *mode;
37 char *new_targets;
38 char *env_targets;
39
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053040 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
Michal Simek19356712016-12-16 13:16:14 +010041 case ZYNQ_BM_QSPI:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053042 mode = "qspi";
Simon Glass6a38e412017-08-03 12:22:09 -060043 env_set("modeboot", "qspiboot");
Michal Simek19356712016-12-16 13:16:14 +010044 break;
45 case ZYNQ_BM_NAND:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053046 mode = "nand";
Simon Glass6a38e412017-08-03 12:22:09 -060047 env_set("modeboot", "nandboot");
Michal Simek19356712016-12-16 13:16:14 +010048 break;
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053049 case ZYNQ_BM_NOR:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053050 mode = "nor";
Simon Glass6a38e412017-08-03 12:22:09 -060051 env_set("modeboot", "norboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053052 break;
53 case ZYNQ_BM_SD:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053054 mode = "mmc";
Simon Glass6a38e412017-08-03 12:22:09 -060055 env_set("modeboot", "sdboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053056 break;
57 case ZYNQ_BM_JTAG:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053058 mode = "pxe dhcp";
Simon Glass6a38e412017-08-03 12:22:09 -060059 env_set("modeboot", "jtagboot");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053060 break;
61 default:
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053062 mode = "";
Simon Glass6a38e412017-08-03 12:22:09 -060063 env_set("modeboot", "");
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053064 break;
65 }
66
Siva Durga Prasad Paladugubd75bc12019-01-25 17:06:06 +053067 /*
68 * One terminating char + one byte for space between mode
69 * and default boot_targets
70 */
71 env_targets = env_get("boot_targets");
72 if (env_targets)
73 env_targets_len = strlen(env_targets);
74
75 new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
76 if (!new_targets)
77 return -ENOMEM;
78
79 sprintf(new_targets, "%s %s", mode,
80 env_targets ? env_targets : "");
81
82 env_set("boot_targets", new_targets);
83
Jagannadha Sutradharudu Teki11704c22014-01-09 01:48:21 +053084 return 0;
85}
Michal Simekaf482d52012-09-28 09:56:37 +000086
Michal Simekf4780a72016-04-01 15:56:33 +020087#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
Simon Glass2f949c32017-03-31 08:40:32 -060088int dram_init_banksize(void)
Nathan Rossic12892b2016-12-04 19:33:22 +100089{
Michal Simekd5b7de62017-11-03 15:25:51 +010090 return fdtdec_setup_memory_banksize();
Tom Riniedcfdbd2016-12-09 07:56:54 -050091}
Michal Simekf4780a72016-04-01 15:56:33 +020092
Tom Riniedcfdbd2016-12-09 07:56:54 -050093int dram_init(void)
94{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +053095 if (fdtdec_setup_mem_size_base() != 0)
Nathan Rossi58ea0d82016-12-19 00:03:34 +100096 return -EINVAL;
Tom Riniedcfdbd2016-12-09 07:56:54 -050097
98 zynq_ddrc_init();
99
100 return 0;
Michal Simekf4780a72016-04-01 15:56:33 +0200101}
Michal Simekf4780a72016-04-01 15:56:33 +0200102#else
103int dram_init(void)
104{
Michal Simek1b846212018-04-11 16:12:28 +0200105 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
106 CONFIG_SYS_SDRAM_SIZE);
Michal Simekf4780a72016-04-01 15:56:33 +0200107
Michal Simekf5ff7bc2013-06-17 14:37:01 +0200108 zynq_ddrc_init();
109
Michal Simekaf482d52012-09-28 09:56:37 +0000110 return 0;
111}
Michal Simekf4780a72016-04-01 15:56:33 +0200112#endif