blob: f24e9ff5ee02ca939593ae99a00ea8aae354a3b2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Álvaro Fernández Rojasdbb6baf2018-02-04 21:10:13 +01002/*
Álvaro Fernández Rojasf02a81a2018-03-22 19:39:42 +01003 * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojasdbb6baf2018-02-04 21:10:13 +01004 *
5 * Derived from linux/arch/mips/bcm63xx/usb-common.c:
6 * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright 2013 Florian Fainelli <florian@openwrt.org>
Álvaro Fernández Rojasdbb6baf2018-02-04 21:10:13 +01008 */
9
10#include <common.h>
11#include <clk.h>
12#include <dm.h>
13#include <generic-phy.h>
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070015#include <malloc.h>
Álvaro Fernández Rojasdbb6baf2018-02-04 21:10:13 +010016#include <power-domain.h>
17#include <reset.h>
18#include <asm/io.h>
19#include <dm/device.h>
20
21/* USBH PLL Control register */
22#define USBH_PLL_REG 0x18
23#define USBH_PLL_IDDQ_PWRDN BIT(9)
24#define USBH_PLL_PWRDN_DELAY BIT(10)
25
26/* USBH Swap Control register */
27#define USBH_SWAP_REG 0x1c
28#define USBH_SWAP_OHCI_DATA BIT(0)
29#define USBH_SWAP_OHCI_ENDIAN BIT(1)
30#define USBH_SWAP_EHCI_DATA BIT(3)
31#define USBH_SWAP_EHCI_ENDIAN BIT(4)
32
33/* USBH Setup register */
34#define USBH_SETUP_REG 0x28
35#define USBH_SETUP_IOC BIT(4)
36#define USBH_SETUP_IPP BIT(5)
37
38struct bcm6368_usbh_hw {
39 uint32_t setup_clr;
40 uint32_t pll_clr;
41};
42
43struct bcm6368_usbh_priv {
44 const struct bcm6368_usbh_hw *hw;
45 void __iomem *regs;
46};
47
48static int bcm6368_usbh_init(struct phy *phy)
49{
50 struct bcm6368_usbh_priv *priv = dev_get_priv(phy->dev);
51 const struct bcm6368_usbh_hw *hw = priv->hw;
52
53 /* configure to work in native cpu endian */
54 clrsetbits_be32(priv->regs + USBH_SWAP_REG,
55 USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
56 USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
57
58 /* setup config */
59 if (hw->setup_clr)
60 clrbits_be32(priv->regs + USBH_SETUP_REG, hw->setup_clr);
61
62 setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
63
64 /* enable pll control */
65 if (hw->pll_clr)
66 clrbits_be32(priv->regs + USBH_PLL_REG, hw->pll_clr);
67
68 return 0;
69}
70
71static struct phy_ops bcm6368_usbh_ops = {
72 .init = bcm6368_usbh_init,
73};
74
75static const struct bcm6368_usbh_hw bcm6328_hw = {
76 .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
77 .setup_clr = 0,
78};
79
80static const struct bcm6368_usbh_hw bcm6362_hw = {
81 .pll_clr = 0,
82 .setup_clr = 0,
83};
84
85static const struct bcm6368_usbh_hw bcm6368_hw = {
86 .pll_clr = 0,
87 .setup_clr = 0,
88};
89
90static const struct bcm6368_usbh_hw bcm63268_hw = {
91 .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
92 .setup_clr = USBH_SETUP_IPP,
93};
94
95static const struct udevice_id bcm6368_usbh_ids[] = {
96 {
97 .compatible = "brcm,bcm6328-usbh",
98 .data = (ulong)&bcm6328_hw,
99 }, {
100 .compatible = "brcm,bcm6362-usbh",
101 .data = (ulong)&bcm6362_hw,
102 }, {
103 .compatible = "brcm,bcm6368-usbh",
104 .data = (ulong)&bcm6368_hw,
105 }, {
106 .compatible = "brcm,bcm63268-usbh",
107 .data = (ulong)&bcm63268_hw,
108 }, { /* sentinel */ }
109};
110
111static int bcm6368_usbh_probe(struct udevice *dev)
112{
113 struct bcm6368_usbh_priv *priv = dev_get_priv(dev);
114 const struct bcm6368_usbh_hw *hw =
115 (const struct bcm6368_usbh_hw *)dev_get_driver_data(dev);
116#if defined(CONFIG_POWER_DOMAIN)
117 struct power_domain pwr_dom;
118#endif
119 struct reset_ctl rst_ctl;
120 struct clk clk;
Álvaro Fernández Rojasdbb6baf2018-02-04 21:10:13 +0100121 int ret;
122
Álvaro Fernández Rojasf02a81a2018-03-22 19:39:42 +0100123 priv->regs = dev_remap_addr(dev);
124 if (!priv->regs)
Álvaro Fernández Rojasdbb6baf2018-02-04 21:10:13 +0100125 return -EINVAL;
126
Álvaro Fernández Rojasdbb6baf2018-02-04 21:10:13 +0100127 priv->hw = hw;
128
129 /* enable usbh clock */
130 ret = clk_get_by_name(dev, "usbh", &clk);
131 if (ret < 0)
132 return ret;
133
134 ret = clk_enable(&clk);
135 if (ret < 0)
136 return ret;
137
138 ret = clk_free(&clk);
139 if (ret < 0)
140 return ret;
141
142#if defined(CONFIG_POWER_DOMAIN)
143 /* enable power domain */
144 ret = power_domain_get(dev, &pwr_dom);
145 if (ret < 0)
146 return ret;
147
148 ret = power_domain_on(&pwr_dom);
149 if (ret < 0)
150 return ret;
151
152 ret = power_domain_free(&pwr_dom);
153 if (ret < 0)
154 return ret;
155#endif
156
157 /* perform reset */
158 ret = reset_get_by_index(dev, 0, &rst_ctl);
159 if (ret < 0)
160 return ret;
161
162 ret = reset_deassert(&rst_ctl);
163 if (ret < 0)
164 return ret;
165
166 ret = reset_free(&rst_ctl);
167 if (ret < 0)
168 return ret;
169
170 /* enable usb_ref clock */
171 ret = clk_get_by_name(dev, "usb_ref", &clk);
172 if (!ret) {
173 ret = clk_enable(&clk);
174 if (ret < 0)
175 return ret;
176
177 ret = clk_free(&clk);
178 if (ret < 0)
179 return ret;
180 }
181
182 mdelay(100);
183
184 return 0;
185}
186
187U_BOOT_DRIVER(bcm6368_usbh) = {
188 .name = "bcm6368-usbh",
189 .id = UCLASS_PHY,
190 .of_match = bcm6368_usbh_ids,
191 .ops = &bcm6368_usbh_ops,
192 .priv_auto_alloc_size = sizeof(struct bcm6368_usbh_priv),
193 .probe = bcm6368_usbh_probe,
194};