blob: 54f48b9ba8f9af55279217649ef221ea4cdcc8e2 [file] [log] [blame]
Oliver Grautedafcd992019-09-20 07:08:41 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017-2018 NXP
4 */
5#include <common.h>
6#include <dm.h>
Simon Glass2dc9c342020-05-10 11:40:01 -06007#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Oliver Grautedafcd992019-09-20 07:08:41 +000010#include <spl.h>
11#include <fsl_esdhc.h>
12
13#include <asm/io.h>
14#include <asm/gpio.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/sci/sci.h>
17#include <asm/arch/imx8-pins.h>
18#include <asm/arch/iomux.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
23 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
24 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
25 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
26
27#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
28 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
29 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
30 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
31
32#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
33 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
34 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
35 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
36
37#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
38 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
39 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
40 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
41
42#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
43 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
44 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
45 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
46
47#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
48 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
49 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
50 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
51
52#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
53 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
54 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
55 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
56
57#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
58 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
59 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
60 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
61#ifdef CONFIG_FSL_ESDHC
62
63#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
64#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
65
66static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
67 {USDHC1_BASE_ADDR, 0, 8},
68 {USDHC2_BASE_ADDR, 0, 4},
69 {USDHC3_BASE_ADDR, 0, 4},
70};
71
72static iomux_cfg_t emmc0[] = {
73 SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
74 SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
75 SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
76 SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
77 SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
78 SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
79 SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
80 SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
81 SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
82 SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
83 SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
84 SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
85};
86
87static iomux_cfg_t usdhc2_sd[] = {
88 SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
89 SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
90 SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
91 SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
92 SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
93 SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
94 SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
95 SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
96 SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
97};
98
99int board_mmc_init(bd_t *bis)
100{
101 int i, ret;
102
103 /*
104 * According to the board_mmc_init() the following map is done:
105 * (U-Boot device node) (Physical Port)
106 * mmc0 USDHC1
107 * mmc1 USDHC2
108 * mmc2 USDHC3
109 */
110 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
111 switch (i) {
112 case 0:
113 ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
114 if (ret != SC_ERR_NONE)
115 return ret;
116
117 imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
118 init_clk_usdhc(0);
119 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
120 break;
121 case 1:
122 ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
123 if (ret != SC_ERR_NONE)
124 return ret;
125 ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
126 if (ret != SC_ERR_NONE)
127 return ret;
128
129 imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
130 init_clk_usdhc(2);
131 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
132 gpio_request(USDHC2_CD_GPIO, "sd2_cd");
133 gpio_direction_input(USDHC2_CD_GPIO);
134 break;
135 default:
136 printf("Warning: you configured more USDHC controllers"
137 "(%d) than supported by the board\n", i + 1);
138 return 0;
139 }
140 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
141 if (ret) {
142 printf("Warning: failed to initialize mmc dev %d\n", i);
143 return ret;
144 }
145 }
146
147 return 0;
148}
149
150int board_mmc_getcd(struct mmc *mmc)
151{
152 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
153 int ret = 0;
154
155 switch (cfg->esdhc_base) {
156 case USDHC1_BASE_ADDR:
157 ret = 1;
158 break;
159 case USDHC2_BASE_ADDR:
160 ret = !gpio_get_value(USDHC1_CD_GPIO);
161 break;
162 case USDHC3_BASE_ADDR:
163 ret = !gpio_get_value(USDHC2_CD_GPIO);
164 break;
165 }
166
167 return ret;
168}
169
170#endif /* CONFIG_FSL_ESDHC */
171
172void spl_board_init(void)
173{
174#if defined(CONFIG_SPL_SPI_SUPPORT)
175 if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
176 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
177 puts("Warning: failed to initialize FSPI0\n");
178 }
179 }
180#endif
181
182 puts("Normal Boot\n");
183}
184
185void spl_board_prepare_for_boot(void)
186{
187#if defined(CONFIG_SPL_SPI_SUPPORT)
188 if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
189 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
190 puts("Warning: failed to turn off FSPI0\n");
191 }
192 }
193#endif
194}
195
196#ifdef CONFIG_SPL_LOAD_FIT
197int board_fit_config_name_match(const char *name)
198{
199 /* Just empty function now - can't decide what to choose */
200 debug("%s: %s\n", __func__, name);
201
202 return 0;
203}
204#endif
205
206void board_init_f(ulong dummy)
207{
208 /* Clear global data */
209 memset((void *)gd, 0, sizeof(gd_t));
210
211 arch_cpu_init();
212
213 board_early_init_f();
214
215 timer_init();
216
217 preloader_console_init();
218
219 /* Clear the BSS. */
220 memset(__bss_start, 0, __bss_end - __bss_start);
221
222 board_init_r(NULL, 0);
223}