blob: 3f2ca840dc9506983b31bf78285a845eabfdaae9 [file] [log] [blame]
Simon Glass466c7852019-12-06 21:42:18 -07001// SPDX-License-Identifier: Intel
2/*
3 * Copyright 2019 Google LLC
4 * Written by Simon Glass <sjg@chromium.org>
5 */
6
7#include <common.h>
8#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Simon Glass466c7852019-12-06 21:42:18 -070010#include <spi_flash.h>
11#include <asm/fsp/fsp_support.h>
12#include <asm/fsp2/fsp_internal.h>
13
14/* The amount of the FSP header to probe to obtain what we need */
15#define PROBE_BUF_SIZE 0x180
16
17int fsp_get_header(ulong offset, ulong size, bool use_spi_flash,
18 struct fsp_header **fspp)
19{
20 static efi_guid_t guid = FSP_HEADER_GUID;
21 struct fv_ext_header *exhdr;
22 struct fsp_header *fsp;
23 struct ffs_file_header *file_hdr;
24 struct fv_header *fv;
25 struct raw_section *raw;
26 void *ptr, *base;
27 u8 buf[PROBE_BUF_SIZE];
28 struct udevice *dev;
29 int ret;
30
31 /*
32 * There are quite a very steps to work through all the headers in this
33 * file and the structs have similar names. Turn on debugging if needed
34 * to understand what is going wrong.
35 *
36 * You are in a maze of twisty little headers all alike.
37 */
38 debug("offset=%x buf=%x\n", (uint)offset, (uint)buf);
39 if (use_spi_flash) {
40 ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
41 if (ret)
42 return log_msg_ret("Cannot find flash device", ret);
43 ret = spi_flash_read_dm(dev, offset, PROBE_BUF_SIZE, buf);
44 if (ret)
45 return log_msg_ret("Cannot read flash", ret);
46 } else {
47 memcpy(buf, (void *)offset, PROBE_BUF_SIZE);
48 }
49
50 /* Initalise the FSP base */
51 ptr = buf;
52 fv = ptr;
53
54 /* Check the FV signature, _FVH */
55 debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign);
56 if (fv->sign != EFI_FVH_SIGNATURE)
57 return log_msg_ret("Base FV signature", -EINVAL);
58
59 /* Go to the end of the FV header and align the address */
60 debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off);
61 ptr += fv->ext_hdr_off;
62 exhdr = ptr;
63 ptr += ALIGN(exhdr->ext_hdr_size, 8);
64 debug("ptr=%x\n", ptr - (void *)buf);
65
66 /* Check the FFS GUID */
67 file_hdr = ptr;
68 if (memcmp(&file_hdr->name, &guid, sizeof(guid)))
69 return log_msg_ret("Base FFS GUID", -ENXIO);
70 /* Add the FFS header size to find the raw section header */
71 ptr = file_hdr + 1;
72
73 raw = ptr;
74 debug("raw->type = %x\n", raw->type);
75 if (raw->type != EFI_SECTION_RAW)
76 return log_msg_ret("Section type not RAW", -ENOEXEC);
77
78 /* Add the raw section header size to find the FSP header */
79 ptr = raw + 1;
80 fsp = ptr;
81
82 /* Check the FSPH header */
83 debug("fsp %x\n", (uint)fsp);
84 if (fsp->sign != EFI_FSPH_SIGNATURE)
85 return log_msg_ret("Base FSPH signature", -EACCES);
86
87 base = (void *)fsp->img_base;
88 debug("Image base %x\n", (uint)base);
89 debug("Image addr %x\n", (uint)fsp->fsp_mem_init);
90 if (use_spi_flash) {
91 ret = spi_flash_read_dm(dev, offset, size, base);
92 if (ret)
93 return log_msg_ret("Could not read FPS-M", ret);
94 } else {
95 memcpy(base, (void *)offset, size);
96 }
97 ptr = base + (ptr - (void *)buf);
98 *fspp = ptr;
99
100 return 0;
101}
102
103u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)
104{
105 fsp_notify_f notify;
106 struct fsp_notify_params params;
107 struct fsp_notify_params *params_ptr;
108 u32 status;
109
110 if (!fsp_hdr)
111 fsp_hdr = gd->arch.fsp_s_hdr;
112
113 if (!fsp_hdr)
114 return log_msg_ret("no FSP", -ENOENT);
115
116 notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify);
117 params.phase = phase;
118 params_ptr = &params;
119
120 /*
121 * Use ASM code to ensure correct parameter is on the stack for
122 * FspNotify as U-Boot is using different ABI from FSP
123 */
124 asm volatile (
125 "pushl %1;" /* push notify phase */
126 "call *%%eax;" /* call FspNotify */
127 "addl $4, %%esp;" /* clean up the stack */
128 : "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr)
129 );
130
131 return status;
132}