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git01.mediatek.com / filogic / uboot / 0f2af88cfb48b94e4b5d3a70bab8e194577af316 / . / arch / arm / mach-mediatek / mt7629 / init.c
blob: aa9ff2bdba74c59310ccf93606f567a2f5739023 [file] [log] [blame]
developerf4a079c2018-11-15 10:07:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 */
6
7#include <clk.h>
8#include <common.h>
9#include <dm.h>
10#include <fdtdec.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]11#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame^]12#include <log.h>
developerf4a079c2018-11-15 10:07:52 +0800[diff] [blame]13#include <ram.h>
14#include <asm/arch/misc.h>
15#include <asm/sections.h>
16#include <dm/uclass.h>
17#include <linux/io.h>
18
19#include <dt-bindings/clock/mt7629-clk.h>
20
21#define L2_CFG_BASE 0x10200000
22#define L2_CFG_SIZE 0x1000
23#define L2_SHARE_CFG_MP0 0x7f0
24#define L2_SHARE_MODE_OFF BIT(8)
25
26DECLARE_GLOBAL_DATA_PTR;
27
28int mtk_pll_early_init(void)
29{
30 unsigned long pll_rates[] = {
31 [CLK_APMIXED_ARMPLL] = 1250000000,
32 [CLK_APMIXED_MAINPLL] = 1120000000,
33 [CLK_APMIXED_UNIV2PLL] = 1200000000,
34 [CLK_APMIXED_ETH1PLL] = 500000000,
35 [CLK_APMIXED_ETH2PLL] = 700000000,
36 [CLK_APMIXED_SGMIPLL] = 650000000,
37 };
38 struct udevice *dev;
39 int ret, i;
40
41 ret = uclass_get_device_by_driver(UCLASS_CLK,
42 DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
43 if (ret)
44 return ret;
45
46 /* configure default rate then enable apmixedsys */
47 for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
48 struct clk clk = { .id = i, .dev = dev };
49
50 ret = clk_set_rate(&clk, pll_rates[i]);
51 if (ret)
52 return ret;
53
54 ret = clk_enable(&clk);
55 if (ret)
56 return ret;
57 }
58
59 /* setup mcu bus */
60 ret = uclass_get_device_by_driver(UCLASS_SYSCON,
61 DM_GET_DRIVER(mtk_mcucfg), &dev);
62 if (ret)
63 return ret;
64
65 return 0;
66}
67
68int mtk_soc_early_init(void)
69{
70 struct udevice *dev;
71 int ret;
72
73 /* initialize early clocks */
74 ret = mtk_pll_early_init();
75 if (ret)
76 return ret;
77
78 ret = uclass_first_device_err(UCLASS_RAM, &dev);
79 if (ret)
80 return ret;
81
82 return 0;
83}
84
85int mach_cpu_init(void)
86{
87 void __iomem *base;
88
89 base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
90
91 /* disable L2C shared mode */
92 writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
93
94 return 0;
95}
96
97int dram_init(void)
98{
99 struct ram_info ram;
100 struct udevice *dev;
101 int ret;
102
103 ret = uclass_first_device_err(UCLASS_RAM, &dev);
104 if (ret)
105 return ret;
106
107 ret = ram_get_info(dev, &ram);
108 if (ret)
109 return ret;
110
111 debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
112
113 gd->ram_size = ram.size;
114
115 return 0;
116}
117
118int print_cpuinfo(void)
119{
120 void __iomem *chipid;
121 u32 hwcode, swver;
122
123 chipid = ioremap(VER_BASE, VER_SIZE);
124 hwcode = readl(chipid + APHW_CODE);
125 swver = readl(chipid + APSW_VER);
126
127 printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
128
129 return 0;
130}