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git01.mediatek.com / filogic / uboot / 0f28e18f1e206de5d92c878da06e13f280946f9a / . / arch / x86 / dts / crownbay.dts
blob: 64282303fb8ab71c7e1a4994b637f49b8cd2af42 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Bin Meng115b5e32014-12-12 21:05:24 +0800[diff] [blame]2/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
Bin Meng115b5e32014-12-12 21:05:24 +0800[diff] [blame]4 */
5
6/dts-v1/;
7
Bin Meng51c3b1e2015-05-25 22:35:04 +0800[diff] [blame]8#include <dt-bindings/interrupt-router/intel-irq.h>
9
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]10/include/ "skeleton.dtsi"
Bin Meng82db36c2014-12-24 13:06:38 +0800[diff] [blame]11/include/ "serial.dtsi"
Bin Meng50704d32015-11-12 05:33:05 -0800[diff] [blame]12/include/ "keyboard.dtsi"
Bin Meng0b9461d2019-02-26 01:52:22 -0800[diff] [blame]13/include/ "pcspkr.dtsi"
Bin Mengaf5b8d22018-07-19 03:07:33 -0700[diff] [blame]14/include/ "reset.dtsi"
Bin Meng8800c412015-06-23 12:18:43 +0800[diff] [blame]15/include/ "rtc.dtsi"
Bin Meng115b5e32014-12-12 21:05:24 +0800[diff] [blame]16
Bin Meng8967f632021-07-28 12:00:23 +0800[diff] [blame]17#include "tsc_timer.dtsi"
Simon Glassbee77f62020-11-05 06:32:17 -0700[diff] [blame]18#include "smbios.dtsi"
19
Bin Meng115b5e32014-12-12 21:05:24 +0800[diff] [blame]20/ {
Bin Meng115b5e32014-12-12 21:05:24 +0800[diff] [blame]21 model = "Intel Crown Bay";
22 compatible = "intel,crownbay", "intel,queensbay";
23
Bin Meng60ccd372015-04-15 12:00:11 +0800[diff] [blame]24 aliases {
Bin Meng4f8d4e92016-01-27 00:56:34 -0800[diff] [blame]25 spi0 = &spi;
Bin Meng60ccd372015-04-15 12:00:11 +0800[diff] [blame]26 };
27
Bin Meng115b5e32014-12-12 21:05:24 +0800[diff] [blame]28 config {
29 silent_console = <0>;
30 };
31
Bin Meng3916df52015-06-17 11:15:39 +0800[diff] [blame]32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "cpu-x86";
39 reg = <0>;
40 intel,apic-id = <0>;
41 };
42
43 cpu@1 {
44 device_type = "cpu";
45 compatible = "cpu-x86";
46 reg = <1>;
47 intel,apic-id = <1>;
48 };
49
50 };
51
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]52 chosen {
Bin Meng37e40302014-12-31 16:05:14 +0800[diff] [blame]53 /*
54 * By default the legacy superio serial port is used as the
55 * U-Boot serial console. If we want to use UART from Topcliff
56 * PCH as the console, change this property to &pciuart#.
57 *
58 * For example, stdout-path = &pciuart0 will use the first
59 * UART on Topcliff PCH.
60 */
Bin Mengaea05d82014-12-24 13:06:39 +0800[diff] [blame]61 stdout-path = "/serial";
Bin Meng115b5e32014-12-12 21:05:24 +0800[diff] [blame]62 };
63
Simon Glass8bfe0662014-12-17 15:50:37 +0800[diff] [blame]64 microcode {
65 update@0 {
66#include "microcode/m0220661105_cv.dtsi"
67 };
68 };
69
Bin Meng37e40302014-12-31 16:05:14 +0800[diff] [blame]70 pci {
71 #address-cells = <3>;
72 #size-cells = <2>;
Bin Mengd0e93732015-07-19 00:20:07 +0800[diff] [blame]73 compatible = "pci-x86";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-all;
Bin Mengd0e93732015-07-19 00:20:07 +0800[diff] [blame]75 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
76 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
77 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
Bin Meng37e40302014-12-31 16:05:14 +0800[diff] [blame]78
79 pcie@17,0 {
80 #address-cells = <3>;
81 #size-cells = <2>;
Bin Meng4521a6c2015-08-24 01:14:03 -0700[diff] [blame]82 compatible = "pci-bridge";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-all;
Bin Meng4521a6c2015-08-24 01:14:03 -0700[diff] [blame]84 reg = <0x0000b800 0x0 0x0 0x0 0x0>;
Bin Meng37e40302014-12-31 16:05:14 +0800[diff] [blame]85
86 topcliff@0,0 {
87 #address-cells = <3>;
88 #size-cells = <2>;
Bin Meng4521a6c2015-08-24 01:14:03 -0700[diff] [blame]89 compatible = "pci-bridge";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-all;
Bin Meng4521a6c2015-08-24 01:14:03 -0700[diff] [blame]91 reg = <0x00010000 0x0 0x0 0x0 0x0>;
Bin Meng37e40302014-12-31 16:05:14 +0800[diff] [blame]92
93 pciuart0: uart@a,1 {
94 compatible = "pci8086,8811.00",
95 "pci8086,8811",
96 "pciclass,070002",
97 "pciclass,0700",
Bin Meng20e9e162015-12-07 05:28:13 -0800[diff] [blame]98 "ns16550";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-all;
Bin Meng37e40302014-12-31 16:05:14 +0800[diff] [blame]100 reg = <0x00025100 0x0 0x0 0x0 0x0
101 0x01025110 0x0 0x0 0x0 0x0>;
102 reg-shift = <0>;
103 clock-frequency = <1843200>;
104 current-speed = <115200>;
105 };
106
107 pciuart1: uart@a,2 {
108 compatible = "pci8086,8812.00",
109 "pci8086,8812",
110 "pciclass,070002",
111 "pciclass,0700",
Bin Meng20e9e162015-12-07 05:28:13 -0800[diff] [blame]112 "ns16550";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-all;
Bin Meng37e40302014-12-31 16:05:14 +0800[diff] [blame]114 reg = <0x00025200 0x0 0x0 0x0 0x0
115 0x01025210 0x0 0x0 0x0 0x0>;
116 reg-shift = <0>;
117 clock-frequency = <1843200>;
118 current-speed = <115200>;
119 };
120
121 pciuart2: uart@a,3 {
122 compatible = "pci8086,8813.00",
123 "pci8086,8813",
124 "pciclass,070002",
125 "pciclass,0700",
Bin Meng20e9e162015-12-07 05:28:13 -0800[diff] [blame]126 "ns16550";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-all;
Bin Meng37e40302014-12-31 16:05:14 +0800[diff] [blame]128 reg = <0x00025300 0x0 0x0 0x0 0x0
129 0x01025310 0x0 0x0 0x0 0x0>;
130 reg-shift = <0>;
131 clock-frequency = <1843200>;
132 current-speed = <115200>;
133 };
134
135 pciuart3: uart@a,4 {
136 compatible = "pci8086,8814.00",
137 "pci8086,8814",
138 "pciclass,070002",
139 "pciclass,0700",
Bin Meng20e9e162015-12-07 05:28:13 -0800[diff] [blame]140 "ns16550";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]141 bootph-all;
Bin Meng37e40302014-12-31 16:05:14 +0800[diff] [blame]142 reg = <0x00025400 0x0 0x0 0x0 0x0
143 0x01025410 0x0 0x0 0x0 0x0>;
144 reg-shift = <0>;
145 clock-frequency = <1843200>;
146 current-speed = <115200>;
147 };
148 };
149 };
Bin Meng51c3b1e2015-05-25 22:35:04 +0800[diff] [blame]150
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]151 pch@1f,0 {
Bin Meng51c3b1e2015-05-25 22:35:04 +0800[diff] [blame]152 reg = <0x0000f800 0 0 0 0>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]153 compatible = "intel,pch7";
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]154 #address-cells = <1>;
155 #size-cells = <1>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]156
157 irq-router {
Bin Meng0c9f5942018-06-03 19:04:22 -0700[diff] [blame]158 compatible = "intel,irq-router";
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]159 intel,pirq-config = "pci";
Bin Meng0651f622016-05-07 07:46:15 -0700[diff] [blame]160 intel,actl-addr = <0x58>;
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]161 intel,pirq-link = <0x60 8>;
162 intel,pirq-mask = <0xcee0>;
163 intel,pirq-routing = <
164 /* TunnelCreek PCI devices */
165 PCI_BDF(0, 2, 0) INTA PIRQE
166 PCI_BDF(0, 3, 0) INTA PIRQF
167 PCI_BDF(0, 23, 0) INTA PIRQA
168 PCI_BDF(0, 23, 0) INTB PIRQB
169 PCI_BDF(0, 23, 0) INTC PIRQC
170 PCI_BDF(0, 23, 0) INTD PIRQD
171 PCI_BDF(0, 24, 0) INTA PIRQB
172 PCI_BDF(0, 24, 0) INTB PIRQC
173 PCI_BDF(0, 24, 0) INTC PIRQD
174 PCI_BDF(0, 24, 0) INTD PIRQA
175 PCI_BDF(0, 25, 0) INTA PIRQC
176 PCI_BDF(0, 25, 0) INTB PIRQD
177 PCI_BDF(0, 25, 0) INTC PIRQA
178 PCI_BDF(0, 25, 0) INTD PIRQB
179 PCI_BDF(0, 26, 0) INTA PIRQD
180 PCI_BDF(0, 26, 0) INTB PIRQA
181 PCI_BDF(0, 26, 0) INTC PIRQB
182 PCI_BDF(0, 26, 0) INTD PIRQC
183 PCI_BDF(0, 27, 0) INTA PIRQG
184 /*
185 * Topcliff PCI devices
186 *
187 * Note on the Crown Bay board, Topcliff
188 * chipset is connected to TunnelCreek
189 * PCIe port 0, so its bus number is 1
190 * for its PCIe port and 2 for its PCI
191 * devices per U-Boot current PCI bus
192 * enumeration algorithm.
193 */
194 PCI_BDF(1, 0, 0) INTA PIRQA
195 PCI_BDF(2, 0, 1) INTA PIRQA
196 PCI_BDF(2, 0, 2) INTA PIRQA
197 PCI_BDF(2, 2, 0) INTB PIRQD
198 PCI_BDF(2, 2, 1) INTB PIRQD
199 PCI_BDF(2, 2, 2) INTB PIRQD
200 PCI_BDF(2, 2, 3) INTB PIRQD
201 PCI_BDF(2, 2, 4) INTB PIRQD
202 PCI_BDF(2, 4, 0) INTC PIRQC
203 PCI_BDF(2, 4, 1) INTC PIRQC
204 PCI_BDF(2, 6, 0) INTD PIRQB
205 PCI_BDF(2, 8, 0) INTA PIRQA
206 PCI_BDF(2, 8, 1) INTA PIRQA
207 PCI_BDF(2, 8, 2) INTA PIRQA
208 PCI_BDF(2, 8, 3) INTA PIRQA
209 PCI_BDF(2, 10, 0) INTB PIRQD
210 PCI_BDF(2, 10, 1) INTB PIRQD
211 PCI_BDF(2, 10, 2) INTB PIRQD
212 PCI_BDF(2, 10, 3) INTB PIRQD
213 PCI_BDF(2, 10, 4) INTB PIRQD
214 PCI_BDF(2, 12, 0) INTC PIRQC
215 PCI_BDF(2, 12, 1) INTC PIRQC
216 PCI_BDF(2, 12, 2) INTC PIRQC
217 PCI_BDF(2, 12, 3) INTC PIRQC
218 PCI_BDF(2, 12, 4) INTC PIRQC
219 >;
220 };
221
Bin Meng4f8d4e92016-01-27 00:56:34 -0800[diff] [blame]222 spi: spi {
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]223 #address-cells = <1>;
224 #size-cells = <0>;
Bin Mengd9406672016-02-01 01:40:37 -0800[diff] [blame]225 compatible = "intel,ich7-spi";
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]226 spi-flash@0 {
227 reg = <0>;
228 compatible = "sst,25vf016b",
Neil Armstrongf6625b42019-02-10 10:16:21 +0000[diff] [blame]229 "jedec,spi-nor";
Simon Glass32761632016-01-18 20:19:21 -0700[diff] [blame]230 memory-map = <0xffe00000 0x00200000>;
231 };
232 };
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]233
234 gpioa {
235 compatible = "intel,ich6-gpio";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]236 bootph-all;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]237 reg = <0 0x20>;
238 bank-name = "A";
239 };
240
241 gpiob {
242 compatible = "intel,ich6-gpio";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]243 bootph-all;
Bin Meng6e916cc2016-02-01 01:40:47 -0800[diff] [blame]244 reg = <0x20 0x20>;
245 bank-name = "B";
246 };
Bin Meng51c3b1e2015-05-25 22:35:04 +0800[diff] [blame]247 };
Bin Meng37e40302014-12-31 16:05:14 +0800[diff] [blame]248 };
249
Bin Meng115b5e32014-12-12 21:05:24 +0800[diff] [blame]250};