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git01.mediatek.com / filogic / uboot / 0f0173daf470bc450606cd2ba5a6a00eac043f95 / . / board / freescale / ls2080ardb / README
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York Sune12abcb2015-03-20 19:28:24 -0700[diff] [blame]1Overview
2--------
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530[diff] [blame]3The LS2080A Reference Design (RDB) is a high-performance computing,
Priyanka Jain4a6f1732016-11-17 12:29:55 +0530[diff] [blame]4evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
York Sune12abcb2015-03-20 19:28:24 -0700[diff] [blame]5Layerscape Architecture processor.
6
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]7The LS2081A Reference Design (RDB) is a high-performance computing,
8evaluation, and development platform that supports the QorIQ LS2081A
9Layerscape Architecture processor.More details in below sections
10
11LS2080A, LS2088A, LS2081A SoC Overview
12--------------------------------------
Priyanka Jain4a6f1732016-11-17 12:29:55 +0530[diff] [blame]13Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]14LS2081A, LS2088A SoC overview.
York Sune12abcb2015-03-20 19:28:24 -0700[diff] [blame]15
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530[diff] [blame]16 LS2080ARDB board Overview
York Sune12abcb2015-03-20 19:28:24 -0700[diff] [blame]17 -----------------------
18 - SERDES Connections, 16 lanes supporting:
19 - PCI Express - 3.0
20 - SATA 3.0
21 - XFI
22 - DDR Controller
23 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
24 chip-selects and two DIMM connectors. Support is up to 2133MT/s.
25 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
26 and two DIMM connectors. Support is up to 1600MT/s.
27 -IFC/Local Bus
28 - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
29 - 128 MB NOR flash 16-bit data bus
30 - One 2 GB NAND flash with ECC support
31 - CPLD connection
32 - USB 3.0
33 - Two high speed USB 3.0 ports
34 - First USB 3.0 port configured as Host with Type-A connector
35 - Second USB 3.0 port configured as OTG with micro-AB connector
36 - SDHC adapter
37 - SD Card Rev 2.0 and Rev 3.0
38 - DSPI
39 - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
40 - 4 I2C controllers
41 - Two SATA onboard connectors
42 - UART
43 - ARM JTAG support
44
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530[diff] [blame]45 LS2081ARDB board Overview
46 -------------------------
47 LS2081ARDB board is similar to LS2080ARDB board
48 with few differences like
49 - Hosts LS2081A SoC
50 - Default boot source is QSPI-boot
51 - Does not have IFC interface
52 - RTC and QSPI flash devices are different
53 - Provides QIXIS access via I2C
54
York Sune12abcb2015-03-20 19:28:24 -0700[diff] [blame]55Memory map from core's view
56----------------------------
570x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
580x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
590x00_1800_0000 .. 0x00_181F_FFFF OCRAM
Priyanka Jain7d05b992017-04-28 10:41:35 +0530[diff] [blame]600x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1
York Sune12abcb2015-03-20 19:28:24 -0700[diff] [blame]610x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
620x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
630x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
640x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
65
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame]66Other addresses are either reserved, or not used directly by U-Boot.
York Sune12abcb2015-03-20 19:28:24 -0700[diff] [blame]67This list should be updated when more addresses are used.
68
69IFC region map from core's view
70-------------------------------
71During boot i.e. IFC Region #1:-
72 0x30000000 - 0x37ffffff : 128MB : NOR flash
73 0x3C000000 - 0x40000000 : 64MB : CPLD
74
75After relocate to DDR i.e. IFC Region #2:-
76 0x5_1000_0000..0x5_1fff_ffff Memory Hole
77 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB)
78 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
79 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
80 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
81
82Booting Options
83---------------
84a) NOR boot
85b) NAND boot
Priyanka Jain7d05b992017-04-28 10:41:35 +0530[diff] [blame]86c) QSPI boot
87
Santan Kumar0f0173d2017-04-28 12:47:24 +0530[diff] [blame^]88Memory map for NOR boot
89-------------------------
90Image Flash Offset
91RCW+PBI 0x00000000
92Boot firmware (U-Boot) 0x00100000
93Boot firmware Environment 0x00300000
94PPA firmware 0x00400000
95Cortina PHY firmware 0x00980000
96DPAA2 MC 0x00A00000
97DPAA2 DPL 0x00D00000
98DPAA2 DPC 0x00E00000
99Kernel.itb 0x01000000
100
Priyanka Jain7d05b992017-04-28 10:41:35 +0530[diff] [blame]101cfg_rcw_src switches needs to be changed for booting from different option.
102Refer to board documentation for correct switch setting.
103
104QSPI boot details
105===================
106Supported only for
107 LS2088ARDB RevF board with LS2088A SoC.
108
109Images needs to be copied to QSPI flash
110as per memory map given below.
111
112Memory map for QSPI flash
113-------------------------
114Image Flash Offset
115RCW+PBI 0x00000000
116Boot firmware (U-Boot) 0x00100000
117Boot firmware Environment 0x00300000
118PPA firmware 0x00400000
119Cortina PHY firmware 0x00980000
120DPAA2 MC 0x00A00000
121DPAA2 DPL 0x00D00000
122DPAA2 DPC 0x00E00000
123Kernel.itb 0x01000000
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530[diff] [blame]124
125Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
126-------------------------------------------------------------------
127One needs to use appropriate bootargs to boot Linux flavors which do
128not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
129below:
130
131=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
132 earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
133 hugepages=16 mem=2048M'
134