| Ashok Reddy Soma | 0ecc45a | 2023-06-14 06:13:49 -0600 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * dts file for Xilinx Versal NET Mini QSPI Configuration |
| 4 | * |
| 5 | * (C) Copyright 2023, Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * Michal Simek <michal.simek@amd.com> |
| 8 | * Ashok Reddy Soma <ashok.reddy.soma@amd.com> |
| 9 | */ |
| 10 | |
| 11 | /dts-v1/; |
| 12 | |
| 13 | / { |
| 14 | compatible = "xlnx,versal-net-mini"; |
| 15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; |
| 17 | model = "Xilinx Versal NET MINI QSPI"; |
| 18 | |
| 19 | aliases { |
| 20 | serial0 = &dcc; |
| 21 | spi0 = &qspi; |
| 22 | }; |
| 23 | |
| 24 | chosen { |
| 25 | stdout-path = "serial0:115200"; |
| 26 | }; |
| 27 | |
| 28 | memory@bbf00000 { |
| 29 | device_type = "memory"; |
| 30 | reg = <0 0xbbf00000 0 0x100000>; |
| 31 | }; |
| 32 | |
| 33 | clk150: clk150 { |
| 34 | compatible = "fixed-clock"; |
| 35 | #clock-cells = <0>; |
| 36 | clock-frequency = <150000000>; |
| 37 | }; |
| 38 | |
| 39 | dcc: dcc { |
| 40 | compatible = "arm,dcc"; |
| 41 | status = "okay"; |
| 42 | bootph-all; |
| 43 | }; |
| 44 | |
| 45 | amba: amba { |
| 46 | bootph-all; |
| 47 | compatible = "simple-bus"; |
| 48 | #address-cells = <2>; |
| 49 | #size-cells = <2>; |
| 50 | ranges; |
| 51 | |
| 52 | qspi: spi@f1030000 { |
| 53 | compatible = "xlnx,versal-qspi-1.0"; |
| 54 | status = "okay"; |
| 55 | clock-names = "ref_clk", "pclk"; |
| 56 | num-cs = <1>; |
| 57 | reg = <0 0xf1030000 0 0x1000>; |
| 58 | #address-cells = <1>; |
| 59 | #size-cells = <0>; |
| 60 | clocks = <&clk150>, <&clk150>; |
| 61 | |
| 62 | flash0: flash@0 { |
| 63 | compatible = "n25q512a", "micron,m25p80", |
| 64 | "jedec,spi-nor"; |
| 65 | reg = <0>; |
| 66 | spi-tx-bus-width = <4>; |
| 67 | spi-rx-bus-width = <4>; |
| 68 | spi-max-frequency = <20000000>; |
| 69 | }; |
| 70 | }; |
| 71 | }; |
| 72 | }; |