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git01.mediatek.com / filogic / uboot / 0eb3a620d7b10f36e9287dd6ad8b6142864a632d / . / drivers / rtc / davinci.c
blob: 99ae31e2a5f219868c7854076291e32b5e3b361d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]2/*
3 * (C) Copyright 2011 DENX Software Engineering GmbH
4 * Heiko Schocher <hs@denx.de>
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]5 */
6#include <common.h>
7#include <command.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]8#include <log.h>
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]9#include <rtc.h>
10#include <asm/io.h>
Tom Rini56424eb2013-08-28 09:00:28 -0400[diff] [blame]11#include <asm/davinci_rtc.h>
Dario Binacchid898c8b2021-06-02 22:37:59 +0200[diff] [blame]12#include <asm/arch/hardware.h>
Simon Glassdbd79542020-05-10 11:40:11 -0600[diff] [blame]13#include <linux/delay.h>
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]14
Dario Binacchid898c8b2021-06-02 22:37:59 +0200[diff] [blame]15#if !defined(RTC_BASE) && defined(DAVINCI_RTC_BASE)
16#define RTC_BASE DAVINCI_RTC_BASE
17#endif
18
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]19int rtc_get(struct rtc_time *tmp)
20{
Dario Binacchid898c8b2021-06-02 22:37:59 +0200[diff] [blame]21 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]22 unsigned long sec, min, hour, mday, wday, mon_cent, year;
23 unsigned long status;
24
Dario Binacchi0eb3a622021-06-02 22:38:00 +0200[diff] [blame^]25 status = readb(&rtc->status);
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]26 if ((status & RTC_STATE_RUN) != RTC_STATE_RUN) {
27 printf("RTC doesn't run\n");
28 return -1;
29 }
30 if ((status & RTC_STATE_BUSY) == RTC_STATE_BUSY)
31 udelay(20);
32
Dario Binacchi0eb3a622021-06-02 22:38:00 +0200[diff] [blame^]33 sec = readb(&rtc->second);
34 min = readb(&rtc->minutes);
35 hour = readb(&rtc->hours);
36 mday = readb(&rtc->day);
37 wday = readb(&rtc->dotw);
38 mon_cent = readb(&rtc->month);
39 year = readb(&rtc->year);
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]40
41 debug("Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
42 "hr: %02lx min: %02lx sec: %02lx\n",
43 year, mon_cent, mday, wday,
44 hour, min, sec);
45
46 tmp->tm_sec = bcd2bin(sec & 0x7F);
47 tmp->tm_min = bcd2bin(min & 0x7F);
48 tmp->tm_hour = bcd2bin(hour & 0x3F);
49 tmp->tm_mday = bcd2bin(mday & 0x3F);
50 tmp->tm_mon = bcd2bin(mon_cent & 0x1F);
51 tmp->tm_year = bcd2bin(year) + 2000;
52 tmp->tm_wday = bcd2bin(wday & 0x07);
53 tmp->tm_yday = 0;
54 tmp->tm_isdst = 0;
55
56 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
57 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
58 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
59
60 return 0;
61}
62
63int rtc_set(struct rtc_time *tmp)
64{
Dario Binacchid898c8b2021-06-02 22:37:59 +0200[diff] [blame]65 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]66
67 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
68 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
69 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Dario Binacchi0eb3a622021-06-02 22:38:00 +0200[diff] [blame^]70 writeb(bin2bcd(tmp->tm_year % 100), &rtc->year);
71 writeb(bin2bcd(tmp->tm_mon), &rtc->month);
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]72
Dario Binacchi0eb3a622021-06-02 22:38:00 +0200[diff] [blame^]73 writeb(bin2bcd(tmp->tm_wday), &rtc->dotw);
74 writeb(bin2bcd(tmp->tm_mday), &rtc->day);
75 writeb(bin2bcd(tmp->tm_hour), &rtc->hours);
76 writeb(bin2bcd(tmp->tm_min), &rtc->minutes);
77 writeb(bin2bcd(tmp->tm_sec), &rtc->second);
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]78 return 0;
79}
80
81void rtc_reset(void)
82{
Dario Binacchid898c8b2021-06-02 22:37:59 +0200[diff] [blame]83 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]84
85 /* run RTC counter */
Dario Binacchi0eb3a622021-06-02 22:38:00 +0200[diff] [blame^]86 writeb(0x01, &rtc->ctrl);
Heiko Schocher62f3ec72011-09-14 19:48:23 +0000[diff] [blame]87}