blob: 324eb6ce15bfef1e43858b73a1127be876dde6aa [file] [log] [blame]
Heiko Schocherac1956e2006-04-20 08:42:42 +02001/*
2 * Configuation settings for the BuS EB+MCF-EV123 boards.
3 *
4 * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef _CONFIG_EB_MCF_EV123_H_
26#define _CONFIG_EB_MCF_EV123_H_
27
28#define CONFIG_EB_MCF_EV123
29
Heiko Schocherac1956e2006-04-20 08:42:42 +020030#undef CFG_HALT_BEFOR_RAM_JUMP
Wolfgang Denkf7290752006-06-10 22:00:40 +020031
Heiko Schocherac1956e2006-04-20 08:42:42 +020032/*
33 * High Level Configuration Options (easy to change)
34 */
35
36#define CONFIG_MCF52x2 /* define processor family */
37#define CONFIG_M5282 /* define processor type */
38
39#define CONFIG_MISC_INIT_R
40
TsiChungLiewceaf3332007-08-15 19:55:10 -050041#define CONFIG_MCFUART
42#define CFG_UART_PORT (0)
Heiko Schocherac1956e2006-04-20 08:42:42 +020043#define CONFIG_BAUDRATE 9600
44#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
45
46#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
47
48#define CONFIG_BOOTCOMMAND "printenv"
49
50/* Configuration for environment
51 * Environment is embedded in u-boot in the second sector of the flash
52 */
53#ifndef CONFIG_MONITOR_IS_IN_RAM
54#define CFG_ENV_ADDR 0xF003C000 /* End of 256K */
55#define CFG_ENV_SECT_SIZE 0x4000
56#define CFG_ENV_IS_IN_FLASH 1
57/*
58#define CFG_ENV_IS_EMBEDDED 1
59#define CFG_ENV_ADDR_REDUND 0xF0018000
60#define CFG_ENV_SECT_SIZE_REDUND 0x4000
61*/
62#else
63#define CFG_ENV_ADDR 0xFFE04000
64#define CFG_ENV_SECT_SIZE 0x2000
65#define CFG_ENV_IS_IN_FLASH 1
66#endif
67
Heiko Schocherac1956e2006-04-20 08:42:42 +020068
Jon Loeligerdbb2b542007-07-07 20:56:05 -050069/*
Jon Loeligerf5709d12007-07-10 09:02:57 -050070 * BOOTP options
71 */
72#define CONFIG_BOOTP_BOOTFILESIZE
73#define CONFIG_BOOTP_BOOTPATH
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76
77
78/*
Jon Loeligerdbb2b542007-07-07 20:56:05 -050079 * Command line configuration.
80 */
81#include <config_cmd_default.h>
82
83#undef CONFIG_CMD_LOADB
TsiChungLiewceaf3332007-08-15 19:55:10 -050084#define CONFIG_CMD_MII
85#define CONFIG_CMD_NET
Jon Loeligerdbb2b542007-07-07 20:56:05 -050086
TsiChung Liew26c9f3c2008-07-09 15:21:44 -050087#define CONFIG_MCFTMR
88
TsiChungLiewceaf3332007-08-15 19:55:10 -050089#define CONFIG_MCFFEC
90#ifdef CONFIG_MCFFEC
91# define CONFIG_NET_MULTI 1
92# define CONFIG_MII 1
TsiChung Liewb3162452008-03-30 01:22:13 -050093# define CONFIG_MII_INIT 1
TsiChungLiewceaf3332007-08-15 19:55:10 -050094# define CFG_DISCOVER_PHY
95# define CFG_RX_ETH_BUFFER 8
96# define CFG_FAULT_ECHO_LINK_DOWN
97
98# define CFG_FEC0_PINMUX 0
99# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
Wolfgang Denka1be4762008-05-20 16:00:29 +0200100# define MCFFEC_TOUT_LOOP 50000
TsiChungLiewceaf3332007-08-15 19:55:10 -0500101/* If CFG_DISCOVER_PHY is not defined - hardcoded */
102# ifndef CFG_DISCOVER_PHY
103# define FECDUPLEX FULL
104# define FECSPEED _100BASET
105# else
106# ifndef CFG_FAULT_ECHO_LINK_DOWN
107# define CFG_FAULT_ECHO_LINK_DOWN
108# endif
109# endif /* CFG_DISCOVER_PHY */
110#endif
111
112#ifdef CONFIG_MCFFEC
113# define CONFIG_ETHADDR 00:CF:52:82:EB:01
114# define CONFIG_IPADDR 192.162.1.2
115# define CONFIG_NETMASK 255.255.255.0
116# define CONFIG_SERVERIP 192.162.1.1
117# define CONFIG_GATEWAYIP 192.162.1.1
118# define CONFIG_OVERWRITE_ETHADDR_ONCE
119#endif /* CONFIG_MCFFEC */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200120
121#define CONFIG_BOOTDELAY 5
122#define CFG_PROMPT "\nEV123 U-Boot> "
123#define CFG_LONGHELP /* undef to save memory */
124
Jon Loeligerdbb2b542007-07-07 20:56:05 -0500125#if defined(CONFIG_CMD_KGDB)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200126#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
127#else
128#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
129#endif
130#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
131#define CFG_MAXARGS 16 /* max number of command args */
132#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
133
134#define CFG_LOAD_ADDR 0x20000
135
136#define CFG_MEMTEST_START 0x100000
137#define CFG_MEMTEST_END 0x400000
138/*#define CFG_DRAM_TEST 1 */
139#undef CFG_DRAM_TEST
140
141/* Clock and PLL Configuration */
Wolfgang Denkf7290752006-06-10 22:00:40 +0200142#define CFG_HZ 10000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200143#define CFG_CLK 58982400 /* 9,8304MHz * 6 */
144
145/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
146
Wolfgang Denkf7290752006-06-10 22:00:40 +0200147#define CFG_MFD 0x01 /* PLL Multiplication Factor Devider */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200148#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
149
150/*
151 * Low Level Configuration Settings
152 * (address mappings, register initial values, etc.)
153 * You should know what you are doing if you make changes here.
154 */
155#define CFG_MBAR 0x40000000
156
Heiko Schocherac1956e2006-04-20 08:42:42 +0200157/*-----------------------------------------------------------------------
158 * Definitions for initial stack pointer and data area (in DPRAM)
159 */
160#define CFG_INIT_RAM_ADDR 0x20000000
161#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200162#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200163#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
164#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
165
166/*-----------------------------------------------------------------------
167 * Start addresses for the final memory configuration
168 * (Set up by the startup code)
169 * Please note that CFG_SDRAM_BASE _must_ start at 0
170 */
171#define CFG_SDRAM_BASE1 0x00000000
172#define CFG_SDRAM_SIZE1 16 /* SDRAM size in MB */
173
174/*
175#define CFG_SDRAM_BASE0 CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
176#define CFG_SDRAM_SIZE0 16 */ /* SDRAM size in MB */
177
178#define CFG_SDRAM_BASE CFG_SDRAM_BASE1
179#define CFG_SDRAM_SIZE CFG_SDRAM_SIZE1
180
181#define CFG_FLASH_BASE 0xFFE00000
182#define CFG_INT_FLASH_BASE 0xF0000000
TsiChungLiewceaf3332007-08-15 19:55:10 -0500183#define CFG_INT_FLASH_ENABLE 0x21
Heiko Schocherac1956e2006-04-20 08:42:42 +0200184
185/* If M5282 port is fully implemented the monitor base will be behind
186 * the vector table. */
187#if (TEXT_BASE != CFG_INT_FLASH_BASE)
Wolfgang Denkf7290752006-06-10 22:00:40 +0200188#define CFG_MONITOR_BASE (TEXT_BASE + 0x400)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200189#else
190#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
191#endif
192
193#define CFG_MONITOR_LEN 0x20000
194#define CFG_MALLOC_LEN (256 << 10)
195#define CFG_BOOTPARAMS_LEN 64*1024
196
197/*
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization ??
201 */
202#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
203
204/*-----------------------------------------------------------------------
205 * FLASH organization
206 */
207#define CFG_MAX_FLASH_SECT 35
208#define CFG_MAX_FLASH_BANKS 2
209#define CFG_FLASH_ERASE_TOUT 10000000
210#define CFG_FLASH_PROTECTION
211
212/*-----------------------------------------------------------------------
213 * Cache Configuration
214 */
215#define CFG_CACHELINE_SIZE 16
216
217/*-----------------------------------------------------------------------
218 * Memory bank definitions
219 */
220
221#define CFG_CS0_BASE CFG_FLASH_BASE
222#define CFG_CS0_SIZE 2*1024*1024
223#define CFG_CS0_WIDTH 16
Wolfgang Denka1be4762008-05-20 16:00:29 +0200224#define CFG_CS0_RO 0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200225#define CFG_CS0_WS 6
226
227#define CFG_CS3_BASE 0xE0000000
228#define CFG_CS3_SIZE 1*1024*1024
229#define CFG_CS3_WIDTH 16
Wolfgang Denka1be4762008-05-20 16:00:29 +0200230#define CFG_CS3_RO 0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200231#define CFG_CS3_WS 6
232
233/*-----------------------------------------------------------------------
234 * Port configuration
235 */
236#define CFG_PACNT 0x0000000 /* Port A D[31:24] */
237#define CFG_PADDR 0x0000000
238#define CFG_PADAT 0x0000000
239
240#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
241#define CFG_PBDDR 0x0000000
242#define CFG_PBDAT 0x0000000
243
244#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
245#define CFG_PCDDR 0x0000000
246#define CFG_PCDAT 0x0000000
247
248#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
249#define CFG_PCDDR 0x0000000
250#define CFG_PCDAT 0x0000000
251
252#define CFG_PEHLPAR 0xC0
253#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
254#define CFG_DDRUA 0x05
Wolfgang Denka1be4762008-05-20 16:00:29 +0200255#define CFG_PJPAR 0xFF;
Heiko Schocherac1956e2006-04-20 08:42:42 +0200256
257/*-----------------------------------------------------------------------
258 * CCM configuration
259 */
260
261#define CFG_CCM_SIZ 0
262
263/*---------------------------------------------------------------------*/
264#endif /* _CONFIG_M5282EVB_H */
265/*---------------------------------------------------------------------*/