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git01.mediatek.com / filogic / uboot / 0e9265c798a70e89757a4b27ae7d95e55ca64196 / . / arch / sandbox / dts / test.dts
blob: ad94901fa18304a281d216094e4f0799f02ea9ea [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]15 mmc0 = "/mmc0";
16 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]17 pci0 = &pci0;
18 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]19 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]20 remoteproc1 = &rproc_1;
21 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]22 rtc0 = &rtc_0;
23 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]24 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]25 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]26 testbus3 = "/some-bus";
27 testfdt0 = "/some-bus/c-test@0";
28 testfdt1 = "/some-bus/c-test@1";
29 testfdt3 = "/b-test";
30 testfdt5 = "/some-bus/c-test@5";
31 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +0200[diff] [blame]32 fdt-dummy0 = "/translation-test@8000/dev@0,0";
33 fdt-dummy1 = "/translation-test@8000/dev@1,100";
34 fdt-dummy2 = "/translation-test@8000/dev@2,200";
35 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]36 usb0 = &usb_0;
37 usb1 = &usb_1;
38 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]39 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]40 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]41 };
42
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]43 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]44 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]45 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]46 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]47 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]48 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]49 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
50 <0>, <&gpio_a 12>;
51 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
52 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
53 <&gpio_b 9 0xc 3 2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]54 };
55
56 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]57 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]58 compatible = "not,compatible";
59 };
60
61 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]62 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]63 };
64
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200[diff] [blame]65 bind-test {
66 bind-test-child1 {
67 compatible = "sandbox,phy";
68 #phy-cells = <1>;
69 };
70
71 bind-test-child2 {
72 compatible = "simple-bus";
73 };
74 };
75
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]76 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]77 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]78 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]79 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]80 ping-add = <3>;
81 };
82
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]83 phy_provider0: gen_phy@0 {
84 compatible = "sandbox,phy";
85 #phy-cells = <1>;
86 };
87
88 phy_provider1: gen_phy@1 {
89 compatible = "sandbox,phy";
90 #phy-cells = <0>;
91 broken;
92 };
93
94 gen_phy_user: gen_phy_user {
95 compatible = "simple-bus";
96 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
97 phy-names = "phy1", "phy2", "phy3";
98 };
99
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]100 some-bus {
101 #address-cells = <1>;
102 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]103 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]104 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]105 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]106 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]107 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]108 compatible = "denx,u-boot-fdt-test";
109 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]110 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]111 ping-add = <5>;
112 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]113 c-test@0 {
114 compatible = "denx,u-boot-fdt-test";
115 reg = <0>;
116 ping-expect = <6>;
117 ping-add = <6>;
118 };
119 c-test@1 {
120 compatible = "denx,u-boot-fdt-test";
121 reg = <1>;
122 ping-expect = <7>;
123 ping-add = <7>;
124 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]125 };
126
127 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]128 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]129 ping-expect = <6>;
130 ping-add = <6>;
131 compatible = "google,another-fdt-test";
132 };
133
134 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]135 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]136 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]137 ping-add = <6>;
138 compatible = "google,another-fdt-test";
139 };
140
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]141 f-test {
142 compatible = "denx,u-boot-fdt-test";
143 };
144
145 g-test {
146 compatible = "denx,u-boot-fdt-test";
147 };
148
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200[diff] [blame]149 clocks {
150 clk_fixed: clk-fixed {
151 compatible = "fixed-clock";
152 #clock-cells = <0>;
153 clock-frequency = <1234>;
154 };
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]155 };
156
157 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]158 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]159 #clock-cells = <1>;
160 };
161
162 clk-test {
163 compatible = "sandbox,clk-test";
164 clocks = <&clk_fixed>,
165 <&clk_sandbox 1>,
166 <&clk_sandbox 0>;
167 clock-names = "fixed", "i2c", "spi";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]168 };
169
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]170 eth@10002000 {
171 compatible = "sandbox,eth";
172 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]173 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]174 };
175
176 eth_5: eth@10003000 {
177 compatible = "sandbox,eth";
178 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]179 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]180 };
181
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]182 eth_3: sbe5 {
183 compatible = "sandbox,eth";
184 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]185 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]186 };
187
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]188 eth@10004000 {
189 compatible = "sandbox,eth";
190 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]191 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]192 };
193
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700[diff] [blame]194 firmware {
195 sandbox_firmware: sandbox-firmware {
196 compatible = "sandbox,firmware";
197 };
198 };
199
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]200 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]201 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]202 gpio-controller;
203 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]204 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]205 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]206 };
207
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]208 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]209 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]210 gpio-controller;
211 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]212 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]213 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]214 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]215
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]216 i2c@0 {
217 #address-cells = <1>;
218 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]219 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]220 compatible = "sandbox,i2c";
221 clock-frequency = <100000>;
222 eeprom@2c {
223 reg = <0x2c>;
224 compatible = "i2c-eeprom";
225 emul {
226 compatible = "sandbox,i2c-eeprom";
227 sandbox,filename = "i2c.bin";
228 sandbox,size = <256>;
229 };
230 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]231
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]232 rtc_0: rtc@43 {
233 reg = <0x43>;
234 compatible = "sandbox-rtc";
235 emul {
236 compatible = "sandbox,i2c-rtc";
237 };
238 };
239
240 rtc_1: rtc@61 {
241 reg = <0x61>;
242 compatible = "sandbox-rtc";
243 emul {
244 compatible = "sandbox,i2c-rtc";
245 };
246 };
247
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]248 sandbox_pmic: sandbox_pmic {
249 reg = <0x40>;
250 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]251
252 mc34708: pmic@41 {
253 reg = <0x41>;
254 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]255 };
256
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]257 adc@0 {
258 compatible = "sandbox,adc";
259 vdd-supply = <&buck2>;
260 vss-microvolts = <0>;
261 };
262
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]263 lcd {
264 u-boot,dm-pre-reloc;
265 compatible = "sandbox,lcd-sdl";
266 xres = <1366>;
267 yres = <768>;
268 };
269
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]270 leds {
271 compatible = "gpio-leds";
272
273 iracibble {
274 gpios = <&gpio_a 1 0>;
275 label = "sandbox:red";
276 };
277
278 martinet {
279 gpios = <&gpio_a 2 0>;
280 label = "sandbox:green";
281 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200[diff] [blame]282
283 default_on {
284 gpios = <&gpio_a 5 0>;
285 label = "sandbox:default_on";
286 default-state = "on";
287 };
288
289 default_off {
290 gpios = <&gpio_a 6 0>;
291 label = "sandbox:default_off";
292 default-state = "off";
293 };
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]294 };
295
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]296 mbox: mbox {
297 compatible = "sandbox,mbox";
298 #mbox-cells = <1>;
299 };
300
301 mbox-test {
302 compatible = "sandbox,mbox-test";
303 mboxes = <&mbox 100>, <&mbox 1>;
304 mbox-names = "other", "test";
305 };
306
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]307 cpu-test1 {
308 compatible = "sandbox,cpu_sandbox";
309 };
310
311 cpu-test2 {
312 compatible = "sandbox,cpu_sandbox";
313 };
314
315 cpu-test3 {
316 compatible = "sandbox,cpu_sandbox";
317 };
318
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]319 misc-test {
320 compatible = "sandbox,misc_sandbox";
321 };
322
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]323 mmc2 {
324 compatible = "sandbox,mmc";
325 };
326
327 mmc1 {
328 compatible = "sandbox,mmc";
329 };
330
331 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]332 compatible = "sandbox,mmc";
333 };
334
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]335 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]336 compatible = "sandbox,pci";
337 device_type = "pci";
338 #address-cells = <3>;
339 #size-cells = <2>;
340 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
341 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]342 pci@0,0 {
343 compatible = "pci-generic";
344 reg = <0x0000 0 0 0 0>;
345 emul@0,0 {
346 compatible = "sandbox,swap-case";
347 };
348 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]349 pci@1f,0 {
350 compatible = "pci-generic";
351 reg = <0xf800 0 0 0 0>;
352 emul@1f,0 {
353 compatible = "sandbox,swap-case";
354 };
355 };
356 };
357
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]358 pci1: pci-controller1 {
359 compatible = "sandbox,pci";
360 device_type = "pci";
361 #address-cells = <3>;
362 #size-cells = <2>;
363 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
364 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700[diff] [blame]365 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
366 0x0c 0x00 0x1234 0x5678>;
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]367 };
368
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]369 pci2: pci-controller2 {
370 compatible = "sandbox,pci";
371 device_type = "pci";
372 #address-cells = <3>;
373 #size-cells = <2>;
374 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
375 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
376 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
377 pci@1f,0 {
378 compatible = "pci-generic";
379 reg = <0xf800 0 0 0 0>;
380 emul@1f,0 {
381 compatible = "sandbox,swap-case";
382 };
383 };
384 };
385
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]386 probing {
387 compatible = "simple-bus";
388 test1 {
389 compatible = "denx,u-boot-probe-test";
390 };
391
392 test2 {
393 compatible = "denx,u-boot-probe-test";
394 };
395
396 test3 {
397 compatible = "denx,u-boot-probe-test";
398 };
399
400 test4 {
401 compatible = "denx,u-boot-probe-test";
402 };
403 };
404
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]405 pwrdom: power-domain {
406 compatible = "sandbox,power-domain";
407 #power-domain-cells = <1>;
408 };
409
410 power-domain-test {
411 compatible = "sandbox,power-domain-test";
412 power-domains = <&pwrdom 2>;
413 };
414
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]415 pwm {
416 compatible = "sandbox,pwm";
417 };
418
419 pwm2 {
420 compatible = "sandbox,pwm";
421 };
422
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]423 ram {
424 compatible = "sandbox,ram";
425 };
426
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]427 reset@0 {
428 compatible = "sandbox,warm-reset";
429 };
430
431 reset@1 {
432 compatible = "sandbox,reset";
433 };
434
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]435 resetc: reset-ctl {
436 compatible = "sandbox,reset-ctl";
437 #reset-cells = <1>;
438 };
439
440 reset-ctl-test {
441 compatible = "sandbox,reset-ctl-test";
442 resets = <&resetc 100>, <&resetc 2>;
443 reset-names = "other", "test";
444 };
445
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]446 rproc_1: rproc@1 {
447 compatible = "sandbox,test-processor";
448 remoteproc-name = "remoteproc-test-dev1";
449 };
450
451 rproc_2: rproc@2 {
452 compatible = "sandbox,test-processor";
453 internal-memory-mapped;
454 remoteproc-name = "remoteproc-test-dev2";
455 };
456
Ramon Fried26ed32e2018-07-02 02:57:59 +0300[diff] [blame]457 smem@0 {
458 compatible = "sandbox,smem";
459 };
460
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]461 spi@0 {
462 #address-cells = <1>;
463 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]464 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]465 compatible = "sandbox,spi";
466 cs-gpios = <0>, <&gpio_a 0>;
467 spi.bin@0 {
468 reg = <0>;
469 compatible = "spansion,m25p16", "spi-flash";
470 spi-max-frequency = <40000000>;
471 sandbox,filename = "spi.bin";
472 };
473 };
474
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]475 syscon@0 {
476 compatible = "sandbox,syscon0";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]477 reg = <0x10 4>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]478 };
479
480 syscon@1 {
481 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]482 reg = <0x20 5
483 0x28 6
484 0x30 7
485 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]486 };
487
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900[diff] [blame]488 syscon@2 {
489 compatible = "simple-mfd", "syscon";
490 reg = <0x40 5
491 0x48 6
492 0x50 7
493 0x58 8>;
494 };
495
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]496 timer {
497 compatible = "sandbox,timer";
498 clock-frequency = <1000000>;
499 };
500
Miquel Raynal80938c12018-05-15 11:57:27 +0200[diff] [blame]501 tpm2 {
502 compatible = "sandbox,tpm2";
503 };
504
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]505 uart0: serial {
506 compatible = "sandbox,serial";
507 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]508 };
509
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]510 usb_0: usb@0 {
511 compatible = "sandbox,usb";
512 status = "disabled";
513 hub {
514 compatible = "sandbox,usb-hub";
515 #address-cells = <1>;
516 #size-cells = <0>;
517 flash-stick {
518 reg = <0>;
519 compatible = "sandbox,usb-flash";
520 };
521 };
522 };
523
524 usb_1: usb@1 {
525 compatible = "sandbox,usb";
526 hub {
527 compatible = "usb-hub";
528 usb,device-class = <9>;
529 hub-emul {
530 compatible = "sandbox,usb-hub";
531 #address-cells = <1>;
532 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]533 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]534 reg = <0>;
535 compatible = "sandbox,usb-flash";
536 sandbox,filepath = "testflash.bin";
537 };
538
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]539 flash-stick@1 {
540 reg = <1>;
541 compatible = "sandbox,usb-flash";
542 sandbox,filepath = "testflash1.bin";
543 };
544
545 flash-stick@2 {
546 reg = <2>;
547 compatible = "sandbox,usb-flash";
548 sandbox,filepath = "testflash2.bin";
549 };
550
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]551 keyb@3 {
552 reg = <3>;
553 compatible = "sandbox,usb-keyb";
554 };
555
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]556 };
557 };
558 };
559
560 usb_2: usb@2 {
561 compatible = "sandbox,usb";
562 status = "disabled";
563 };
564
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]565 spmi: spmi@0 {
566 compatible = "sandbox,spmi";
567 #address-cells = <0x1>;
568 #size-cells = <0x1>;
569 pm8916@0 {
570 compatible = "qcom,spmi-pmic";
571 reg = <0x0 0x1>;
572 #address-cells = <0x1>;
573 #size-cells = <0x1>;
574
575 spmi_gpios: gpios@c000 {
576 compatible = "qcom,pm8916-gpio";
577 reg = <0xc000 0x400>;
578 gpio-controller;
579 gpio-count = <4>;
580 #gpio-cells = <2>;
581 gpio-bank-name="spmi";
582 };
583 };
584 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]585
586 wdt0: wdt@0 {
587 compatible = "sandbox,wdt";
588 };
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]589
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]590 axi: axi@0 {
591 compatible = "sandbox,axi";
592 #address-cells = <0x1>;
593 #size-cells = <0x1>;
594 store@0 {
595 compatible = "sandbox,sandbox_store";
596 reg = <0x0 0x400>;
597 };
598 };
599
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]600 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700[diff] [blame]601 #address-cells = <1>;
602 #size-cells = <1>;
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]603 chosen-test {
604 compatible = "denx,u-boot-fdt-test";
605 reg = <9 1>;
606 };
607 };
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]608
609 translation-test@8000 {
610 compatible = "simple-bus";
611 reg = <0x8000 0x4000>;
612
613 #address-cells = <0x2>;
614 #size-cells = <0x1>;
615
616 ranges = <0 0x0 0x8000 0x1000
617 1 0x100 0x9000 0x1000
618 2 0x200 0xA000 0x1000
619 3 0x300 0xB000 0x1000
620 >;
621
622 dev@0,0 {
623 compatible = "denx,u-boot-fdt-dummy";
624 reg = <0 0x0 0x1000>;
625 };
626
627 dev@1,100 {
628 compatible = "denx,u-boot-fdt-dummy";
629 reg = <1 0x100 0x1000>;
630
631 };
632
633 dev@2,200 {
634 compatible = "denx,u-boot-fdt-dummy";
635 reg = <2 0x200 0x1000>;
636 };
637
638
639 noxlatebus@3,300 {
640 compatible = "simple-bus";
641 reg = <3 0x300 0x1000>;
642
643 #address-cells = <0x1>;
644 #size-cells = <0x0>;
645
646 dev@42 {
647 compatible = "denx,u-boot-fdt-dummy";
648 reg = <0x42>;
649 };
650 };
651 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]652
653 osd {
654 compatible = "sandbox,sandbox_osd";
655 };
Tom Rinib93eea72018-09-30 18:16:51 -0400[diff] [blame]656
Mario Sixab664ff2018-07-31 11:44:13 +0200[diff] [blame]657 board {
658 compatible = "sandbox,board_sandbox";
659 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200[diff] [blame]660
661 sandbox_tee {
662 compatible = "sandbox,tee";
663 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]664};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]665
666#include "sandbox_pmic.dtsi"