Michal Simek | 1a79c27 | 2018-03-28 15:43:51 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * dts file for Xilinx ZynqMP ZCU106 |
| 4 | * |
| 5 | * (C) Copyright 2016, Xilinx, Inc. |
| 6 | * |
| 7 | * Michal Simek <michal.simek@xilinx.com> |
| 8 | */ |
| 9 | |
| 10 | /dts-v1/; |
| 11 | |
| 12 | #include "zynqmp.dtsi" |
| 13 | #include "zynqmp-clk-ccf.dtsi" |
| 14 | #include <dt-bindings/input/input.h> |
| 15 | #include <dt-bindings/gpio/gpio.h> |
| 16 | #include <dt-bindings/phy/phy.h> |
| 17 | |
| 18 | / { |
| 19 | model = "ZynqMP ZCU106 RevA"; |
| 20 | compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; |
| 21 | |
| 22 | aliases { |
| 23 | ethernet0 = &gem3; |
| 24 | gpio0 = &gpio; |
| 25 | i2c0 = &i2c0; |
| 26 | i2c1 = &i2c1; |
| 27 | mmc0 = &sdhci1; |
| 28 | rtc0 = &rtc; |
| 29 | serial0 = &uart0; |
| 30 | serial1 = &uart1; |
| 31 | serial2 = &dcc; |
| 32 | spi0 = &qspi; |
| 33 | usb0 = &usb0; |
| 34 | }; |
| 35 | |
| 36 | chosen { |
| 37 | bootargs = "earlycon"; |
| 38 | stdout-path = "serial0:115200n8"; |
| 39 | }; |
| 40 | |
| 41 | memory@0 { |
| 42 | device_type = "memory"; |
| 43 | reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; |
| 44 | }; |
| 45 | |
| 46 | gpio-keys { |
| 47 | compatible = "gpio-keys"; |
Michal Simek | 1a79c27 | 2018-03-28 15:43:51 +0200 | [diff] [blame] | 48 | autorepeat; |
| 49 | sw19 { |
| 50 | label = "sw19"; |
| 51 | gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; |
| 52 | linux,code = <KEY_DOWN>; |
| 53 | gpio-key,wakeup; |
| 54 | autorepeat; |
| 55 | }; |
| 56 | }; |
| 57 | |
| 58 | leds { |
| 59 | compatible = "gpio-leds"; |
| 60 | heartbeat_led { |
| 61 | label = "heartbeat"; |
| 62 | gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; |
| 63 | linux,default-trigger = "heartbeat"; |
| 64 | }; |
| 65 | }; |
| 66 | }; |
| 67 | |
| 68 | &can1 { |
| 69 | status = "okay"; |
| 70 | }; |
| 71 | |
| 72 | &dcc { |
| 73 | status = "okay"; |
| 74 | }; |
| 75 | |
| 76 | &fpd_dma_chan1 { |
| 77 | status = "okay"; |
| 78 | }; |
| 79 | |
| 80 | &fpd_dma_chan2 { |
| 81 | status = "okay"; |
| 82 | }; |
| 83 | |
| 84 | &fpd_dma_chan3 { |
| 85 | status = "okay"; |
| 86 | }; |
| 87 | |
| 88 | &fpd_dma_chan4 { |
| 89 | status = "okay"; |
| 90 | }; |
| 91 | |
| 92 | &fpd_dma_chan5 { |
| 93 | status = "okay"; |
| 94 | }; |
| 95 | |
| 96 | &fpd_dma_chan6 { |
| 97 | status = "okay"; |
| 98 | }; |
| 99 | |
| 100 | &fpd_dma_chan7 { |
| 101 | status = "okay"; |
| 102 | }; |
| 103 | |
| 104 | &fpd_dma_chan8 { |
| 105 | status = "okay"; |
| 106 | }; |
| 107 | |
| 108 | &gem3 { |
| 109 | status = "okay"; |
| 110 | phy-handle = <&phy0>; |
| 111 | phy-mode = "rgmii-id"; |
| 112 | phy0: phy@c { |
| 113 | reg = <0xc>; |
| 114 | ti,rx-internal-delay = <0x8>; |
| 115 | ti,tx-internal-delay = <0xa>; |
| 116 | ti,fifo-depth = <0x1>; |
| 117 | }; |
| 118 | }; |
| 119 | |
| 120 | &gpio { |
| 121 | status = "okay"; |
| 122 | }; |
| 123 | |
| 124 | &gpu { |
| 125 | status = "okay"; |
| 126 | }; |
| 127 | |
| 128 | &i2c0 { |
| 129 | status = "okay"; |
| 130 | clock-frequency = <400000>; |
| 131 | |
| 132 | tca6416_u97: gpio@20 { |
| 133 | compatible = "ti,tca6416"; |
| 134 | reg = <0x20>; |
| 135 | gpio-controller; /* interrupt not connected */ |
| 136 | #gpio-cells = <2>; |
| 137 | /* |
| 138 | * IRQ not connected |
| 139 | * Lines: |
| 140 | * 0 - SFP_SI5328_INT_ALM |
| 141 | * 1 - HDMI_SI5328_INT_ALM |
| 142 | * 5 - IIC_MUX_RESET_B |
| 143 | * 6 - GEM3_EXP_RESET_B |
| 144 | * 10 - FMC_HPC0_PRSNT_M2C_B |
| 145 | * 11 - FMC_HPC1_PRSNT_M2C_B |
| 146 | * 2-4, 7, 12-17 - not connected |
| 147 | */ |
| 148 | }; |
| 149 | |
| 150 | tca6416_u61: gpio@21 { |
| 151 | compatible = "ti,tca6416"; |
| 152 | reg = <0x21>; |
| 153 | gpio-controller; |
| 154 | #gpio-cells = <2>; |
| 155 | /* |
| 156 | * IRQ not connected |
| 157 | * Lines: |
| 158 | * 0 - VCCPSPLL_EN |
| 159 | * 1 - MGTRAVCC_EN |
| 160 | * 2 - MGTRAVTT_EN |
| 161 | * 3 - VCCPSDDRPLL_EN |
| 162 | * 4 - MIO26_PMU_INPUT_LS |
| 163 | * 5 - PL_PMBUS_ALERT |
| 164 | * 6 - PS_PMBUS_ALERT |
| 165 | * 7 - MAXIM_PMBUS_ALERT |
| 166 | * 10 - PL_DDR4_VTERM_EN |
| 167 | * 11 - PL_DDR4_VPP_2V5_EN |
| 168 | * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON |
| 169 | * 13 - PS_DIMM_SUSPEND_EN |
| 170 | * 14 - PS_DDR4_VTERM_EN |
| 171 | * 15 - PS_DDR4_VPP_2V5_EN |
| 172 | * 16 - 17 - not connected |
| 173 | */ |
| 174 | }; |
| 175 | |
| 176 | i2c-mux@75 { /* u60 */ |
| 177 | compatible = "nxp,pca9544"; |
| 178 | #address-cells = <1>; |
| 179 | #size-cells = <0>; |
| 180 | reg = <0x75>; |
| 181 | i2c@0 { |
| 182 | #address-cells = <1>; |
| 183 | #size-cells = <0>; |
| 184 | reg = <0>; |
| 185 | /* PS_PMBUS */ |
| 186 | ina226@40 { /* u76 */ |
| 187 | compatible = "ti,ina226"; |
| 188 | reg = <0x40>; |
| 189 | shunt-resistor = <5000>; |
| 190 | }; |
| 191 | ina226@41 { /* u77 */ |
| 192 | compatible = "ti,ina226"; |
| 193 | reg = <0x41>; |
| 194 | shunt-resistor = <5000>; |
| 195 | }; |
| 196 | ina226@42 { /* u78 */ |
| 197 | compatible = "ti,ina226"; |
| 198 | reg = <0x42>; |
| 199 | shunt-resistor = <5000>; |
| 200 | }; |
| 201 | ina226@43 { /* u87 */ |
| 202 | compatible = "ti,ina226"; |
| 203 | reg = <0x43>; |
| 204 | shunt-resistor = <5000>; |
| 205 | }; |
| 206 | ina226@44 { /* u85 */ |
| 207 | compatible = "ti,ina226"; |
| 208 | reg = <0x44>; |
| 209 | shunt-resistor = <5000>; |
| 210 | }; |
| 211 | ina226@45 { /* u86 */ |
| 212 | compatible = "ti,ina226"; |
| 213 | reg = <0x45>; |
| 214 | shunt-resistor = <5000>; |
| 215 | }; |
| 216 | ina226@46 { /* u93 */ |
| 217 | compatible = "ti,ina226"; |
| 218 | reg = <0x46>; |
| 219 | shunt-resistor = <5000>; |
| 220 | }; |
| 221 | ina226@47 { /* u88 */ |
| 222 | compatible = "ti,ina226"; |
| 223 | reg = <0x47>; |
| 224 | shunt-resistor = <5000>; |
| 225 | }; |
| 226 | ina226@4a { /* u15 */ |
| 227 | compatible = "ti,ina226"; |
| 228 | reg = <0x4a>; |
| 229 | shunt-resistor = <5000>; |
| 230 | }; |
| 231 | ina226@4b { /* u92 */ |
| 232 | compatible = "ti,ina226"; |
| 233 | reg = <0x4b>; |
| 234 | shunt-resistor = <5000>; |
| 235 | }; |
| 236 | }; |
| 237 | i2c@1 { |
| 238 | #address-cells = <1>; |
| 239 | #size-cells = <0>; |
| 240 | reg = <1>; |
| 241 | /* PL_PMBUS */ |
| 242 | ina226@40 { /* u79 */ |
| 243 | compatible = "ti,ina226"; |
| 244 | reg = <0x40>; |
| 245 | shunt-resistor = <2000>; |
| 246 | }; |
| 247 | ina226@41 { /* u81 */ |
| 248 | compatible = "ti,ina226"; |
| 249 | reg = <0x41>; |
| 250 | shunt-resistor = <5000>; |
| 251 | }; |
| 252 | ina226@42 { /* u80 */ |
| 253 | compatible = "ti,ina226"; |
| 254 | reg = <0x42>; |
| 255 | shunt-resistor = <5000>; |
| 256 | }; |
| 257 | ina226@43 { /* u84 */ |
| 258 | compatible = "ti,ina226"; |
| 259 | reg = <0x43>; |
| 260 | shunt-resistor = <5000>; |
| 261 | }; |
| 262 | ina226@44 { /* u16 */ |
| 263 | compatible = "ti,ina226"; |
| 264 | reg = <0x44>; |
| 265 | shunt-resistor = <5000>; |
| 266 | }; |
| 267 | ina226@45 { /* u65 */ |
| 268 | compatible = "ti,ina226"; |
| 269 | reg = <0x45>; |
| 270 | shunt-resistor = <5000>; |
| 271 | }; |
| 272 | ina226@46 { /* u74 */ |
| 273 | compatible = "ti,ina226"; |
| 274 | reg = <0x46>; |
| 275 | shunt-resistor = <5000>; |
| 276 | }; |
| 277 | ina226@47 { /* u75 */ |
| 278 | compatible = "ti,ina226"; |
| 279 | reg = <0x47>; |
| 280 | shunt-resistor = <5000>; |
| 281 | }; |
| 282 | }; |
| 283 | i2c@2 { |
| 284 | #address-cells = <1>; |
| 285 | #size-cells = <0>; |
| 286 | reg = <2>; |
| 287 | /* MAXIM_PMBUS - 00 */ |
| 288 | max15301@a { /* u46 */ |
| 289 | compatible = "maxim,max15301"; |
| 290 | reg = <0xa>; |
| 291 | }; |
| 292 | max15303@b { /* u4 */ |
| 293 | compatible = "maxim,max15303"; |
| 294 | reg = <0xb>; |
| 295 | }; |
| 296 | max15303@10 { /* u13 */ |
| 297 | compatible = "maxim,max15303"; |
| 298 | reg = <0x10>; |
| 299 | }; |
| 300 | max15301@13 { /* u47 */ |
| 301 | compatible = "maxim,max15301"; |
| 302 | reg = <0x13>; |
| 303 | }; |
| 304 | max15303@14 { /* u7 */ |
| 305 | compatible = "maxim,max15303"; |
| 306 | reg = <0x14>; |
| 307 | }; |
| 308 | max15303@15 { /* u6 */ |
| 309 | compatible = "maxim,max15303"; |
| 310 | reg = <0x15>; |
| 311 | }; |
| 312 | max15303@16 { /* u10 */ |
| 313 | compatible = "maxim,max15303"; |
| 314 | reg = <0x16>; |
| 315 | }; |
| 316 | max15303@17 { /* u9 */ |
| 317 | compatible = "maxim,max15303"; |
| 318 | reg = <0x17>; |
| 319 | }; |
| 320 | max15301@18 { /* u63 */ |
| 321 | compatible = "maxim,max15301"; |
| 322 | reg = <0x18>; |
| 323 | }; |
| 324 | max15303@1a { /* u49 */ |
| 325 | compatible = "maxim,max15303"; |
| 326 | reg = <0x1a>; |
| 327 | }; |
| 328 | max15303@1b { /* u8 */ |
| 329 | compatible = "maxim,max15303"; |
| 330 | reg = <0x1b>; |
| 331 | }; |
| 332 | max15303@1d { /* u18 */ |
| 333 | compatible = "maxim,max15303"; |
| 334 | reg = <0x1d>; |
| 335 | }; |
| 336 | |
| 337 | max20751@72 { /* u95 */ |
| 338 | compatible = "maxim,max20751"; |
| 339 | reg = <0x72>; |
| 340 | }; |
| 341 | max20751@73 { /* u96 */ |
| 342 | compatible = "maxim,max20751"; |
| 343 | reg = <0x73>; |
| 344 | }; |
| 345 | }; |
| 346 | /* Bus 3 is not connected */ |
| 347 | }; |
| 348 | }; |
| 349 | |
| 350 | &i2c1 { |
| 351 | status = "okay"; |
| 352 | clock-frequency = <400000>; |
| 353 | |
| 354 | /* PL i2c via PCA9306 - u45 */ |
| 355 | i2c-mux@74 { /* u34 */ |
| 356 | compatible = "nxp,pca9548"; |
| 357 | #address-cells = <1>; |
| 358 | #size-cells = <0>; |
| 359 | reg = <0x74>; |
| 360 | i2c@0 { |
| 361 | #address-cells = <1>; |
| 362 | #size-cells = <0>; |
| 363 | reg = <0>; |
| 364 | /* |
| 365 | * IIC_EEPROM 1kB memory which uses 256B blocks |
| 366 | * where every block has different address. |
| 367 | * 0 - 256B address 0x54 |
| 368 | * 256B - 512B address 0x55 |
| 369 | * 512B - 768B address 0x56 |
| 370 | * 768B - 1024B address 0x57 |
| 371 | */ |
| 372 | eeprom: eeprom@54 { /* u23 */ |
| 373 | compatible = "atmel,24c08"; |
| 374 | reg = <0x54>; |
| 375 | }; |
| 376 | }; |
| 377 | i2c@1 { |
| 378 | #address-cells = <1>; |
| 379 | #size-cells = <0>; |
| 380 | reg = <1>; |
| 381 | si5341: clock-generator@36 { /* SI5341 - u69 */ |
| 382 | compatible = "si5341"; |
| 383 | reg = <0x36>; |
| 384 | }; |
| 385 | |
| 386 | }; |
| 387 | i2c@2 { |
| 388 | #address-cells = <1>; |
| 389 | #size-cells = <0>; |
| 390 | reg = <2>; |
| 391 | si570_1: clock-generator@5d { /* USER SI570 - u42 */ |
| 392 | #clock-cells = <0>; |
| 393 | compatible = "silabs,si570"; |
| 394 | reg = <0x5d>; |
| 395 | temperature-stability = <50>; |
| 396 | factory-fout = <300000000>; |
| 397 | clock-frequency = <300000000>; |
| 398 | }; |
| 399 | }; |
| 400 | i2c@3 { |
| 401 | #address-cells = <1>; |
| 402 | #size-cells = <0>; |
| 403 | reg = <3>; |
| 404 | si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ |
| 405 | #clock-cells = <0>; |
| 406 | compatible = "silabs,si570"; |
| 407 | reg = <0x5d>; |
| 408 | temperature-stability = <50>; /* copy from zc702 */ |
| 409 | factory-fout = <156250000>; |
| 410 | clock-frequency = <148500000>; |
| 411 | }; |
| 412 | }; |
| 413 | i2c@4 { |
| 414 | #address-cells = <1>; |
| 415 | #size-cells = <0>; |
| 416 | reg = <4>; |
| 417 | si5328: clock-generator@69 {/* SI5328 - u20 */ |
| 418 | compatible = "silabs,si5328"; |
| 419 | reg = <0x69>; |
| 420 | }; |
| 421 | }; |
| 422 | i2c@5 { |
| 423 | #address-cells = <1>; |
| 424 | #size-cells = <0>; |
| 425 | reg = <5>; /* FAN controller */ |
| 426 | temp@4c {/* lm96163 - u128 */ |
| 427 | compatible = "national,lm96163"; |
| 428 | reg = <0x4c>; |
| 429 | }; |
| 430 | }; |
| 431 | /* 6 - 7 unconnected */ |
| 432 | }; |
| 433 | |
| 434 | i2c-mux@75 { |
| 435 | compatible = "nxp,pca9548"; /* u135 */ |
| 436 | #address-cells = <1>; |
| 437 | #size-cells = <0>; |
| 438 | reg = <0x75>; |
| 439 | |
| 440 | i2c@0 { |
| 441 | #address-cells = <1>; |
| 442 | #size-cells = <0>; |
| 443 | reg = <0>; |
| 444 | /* HPC0_IIC */ |
| 445 | }; |
| 446 | i2c@1 { |
| 447 | #address-cells = <1>; |
| 448 | #size-cells = <0>; |
| 449 | reg = <1>; |
| 450 | /* HPC1_IIC */ |
| 451 | }; |
| 452 | i2c@2 { |
| 453 | #address-cells = <1>; |
| 454 | #size-cells = <0>; |
| 455 | reg = <2>; |
| 456 | /* SYSMON */ |
| 457 | }; |
| 458 | i2c@3 { |
| 459 | #address-cells = <1>; |
| 460 | #size-cells = <0>; |
| 461 | reg = <3>; |
| 462 | /* DDR4 SODIMM */ |
| 463 | dev@19 { /* u-boot detection */ |
| 464 | compatible = "xxx"; |
| 465 | reg = <0x19>; |
| 466 | }; |
| 467 | dev@30 { /* u-boot detection */ |
| 468 | compatible = "xxx"; |
| 469 | reg = <0x30>; |
| 470 | }; |
| 471 | dev@35 { /* u-boot detection */ |
| 472 | compatible = "xxx"; |
| 473 | reg = <0x35>; |
| 474 | }; |
| 475 | dev@36 { /* u-boot detection */ |
| 476 | compatible = "xxx"; |
| 477 | reg = <0x36>; |
| 478 | }; |
| 479 | dev@51 { /* u-boot detection - maybe SPD */ |
| 480 | compatible = "xxx"; |
| 481 | reg = <0x51>; |
| 482 | }; |
| 483 | }; |
| 484 | i2c@4 { |
| 485 | #address-cells = <1>; |
| 486 | #size-cells = <0>; |
| 487 | reg = <4>; |
| 488 | /* SEP 3 */ |
| 489 | }; |
| 490 | i2c@5 { |
| 491 | #address-cells = <1>; |
| 492 | #size-cells = <0>; |
| 493 | reg = <5>; |
| 494 | /* SEP 2 */ |
| 495 | }; |
| 496 | i2c@6 { |
| 497 | #address-cells = <1>; |
| 498 | #size-cells = <0>; |
| 499 | reg = <6>; |
| 500 | /* SEP 1 */ |
| 501 | }; |
| 502 | i2c@7 { |
| 503 | #address-cells = <1>; |
| 504 | #size-cells = <0>; |
| 505 | reg = <7>; |
| 506 | /* SEP 0 */ |
| 507 | }; |
| 508 | }; |
| 509 | }; |
| 510 | |
| 511 | &qspi { |
| 512 | status = "okay"; |
| 513 | is-dual = <1>; |
| 514 | flash@0 { |
| 515 | compatible = "m25p80"; /* 32MB */ |
| 516 | #address-cells = <1>; |
| 517 | #size-cells = <1>; |
| 518 | reg = <0x0>; |
| 519 | spi-tx-bus-width = <1>; |
| 520 | spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ |
| 521 | spi-max-frequency = <108000000>; /* Based on DC1 spec */ |
| 522 | partition@qspi-fsbl-uboot { /* for testing purpose */ |
| 523 | label = "qspi-fsbl-uboot"; |
| 524 | reg = <0x0 0x100000>; |
| 525 | }; |
| 526 | partition@qspi-linux { /* for testing purpose */ |
| 527 | label = "qspi-linux"; |
| 528 | reg = <0x100000 0x500000>; |
| 529 | }; |
| 530 | partition@qspi-device-tree { /* for testing purpose */ |
| 531 | label = "qspi-device-tree"; |
| 532 | reg = <0x600000 0x20000>; |
| 533 | }; |
| 534 | partition@qspi-rootfs { /* for testing purpose */ |
| 535 | label = "qspi-rootfs"; |
| 536 | reg = <0x620000 0x5E0000>; |
| 537 | }; |
| 538 | }; |
| 539 | }; |
| 540 | |
| 541 | &rtc { |
| 542 | status = "okay"; |
| 543 | }; |
| 544 | |
| 545 | &sata { |
| 546 | status = "okay"; |
| 547 | /* SATA OOB timing settings */ |
| 548 | ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; |
| 549 | ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; |
| 550 | ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
| 551 | ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
| 552 | ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; |
| 553 | ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; |
| 554 | ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
| 555 | ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
| 556 | phy-names = "sata-phy"; |
| 557 | phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; |
| 558 | }; |
| 559 | |
| 560 | /* SD1 with level shifter */ |
| 561 | &sdhci1 { |
| 562 | status = "okay"; |
| 563 | no-1-8-v; |
| 564 | xlnx,mio_bank = <1>; |
| 565 | }; |
| 566 | |
| 567 | &serdes { |
| 568 | status = "okay"; |
| 569 | }; |
| 570 | |
| 571 | &uart0 { |
| 572 | status = "okay"; |
| 573 | }; |
| 574 | |
| 575 | &uart1 { |
| 576 | status = "okay"; |
| 577 | }; |
| 578 | |
| 579 | /* ULPI SMSC USB3320 */ |
| 580 | &usb0 { |
| 581 | status = "okay"; |
| 582 | }; |
| 583 | |
| 584 | &dwc3_0 { |
| 585 | status = "okay"; |
| 586 | dr_mode = "host"; |
| 587 | snps,usb3_lpm_capable; |
| 588 | phy-names = "usb3-phy"; |
| 589 | phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; |
| 590 | }; |
| 591 | |
| 592 | &watchdog0 { |
| 593 | status = "okay"; |
| 594 | }; |