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git01.mediatek.com / filogic / uboot / 0e4f80011978ec70002f425a78dc0e8b9babe28d / . / board / pm826 / pm826.c
blob: 93bb1b46155e42f58c2e3dec0be91672e73677ac [file] [log] [blame]
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]6 */
7
8#include <common.h>
9#include <ioports.h>
10#include <mpc8260.h>
wdenk28536032003-03-25 16:50:56 +0000[diff] [blame]11#include <pci.h>
Ben Warren052a5ea2008-08-31 20:37:00 -0700[diff] [blame]12#include <netdev.h>
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]13
14/*
15 * I/O Port configuration table
16 *
17 * if conf is 1, then that port pin will be configured at boot time
18 * according to the five values podr/pdir/ppar/psor/pdat for that entry
19 */
20
21const iop_conf_t iop_conf_tab[4][32] = {
22
23 /* Port A configuration */
24 { /* conf ppar psor pdir podr pdat */
25 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
26 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
27 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
28 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
29 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
30 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
31 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */
32 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
33 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
34 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */
35 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
36 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
37 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
38 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
39 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
40 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/
41 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
42 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
43 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */
44 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */
45 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */
46 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */
47 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */
48 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */
49 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
50 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
51 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
52 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
53 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
54 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
55 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
56 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
57 },
58
59 /* Port B configuration */
60 { /* conf ppar psor pdir podr pdat */
wdenkeda42082003-01-17 16:27:01 +0000[diff] [blame]61 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */
62 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */
63 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */
64#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
65#ifdef CONFIG_ETHER_ON_FCC2
66#error "SCC1 conflicts with FCC2"
67#endif
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]68 /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
wdenkeda42082003-01-17 16:27:01 +0000[diff] [blame]69#else
70 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */
71#endif
72 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */
73 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */
74 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */
75 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */
76 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */
77 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */
78 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */
79 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */
80 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */
81 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]82 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
83 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
84 /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
85 /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
86 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
87 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
88 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
89 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
90 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
91 /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */
92 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
93 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
94 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
95 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
96 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
97 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
98 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
99 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
100 },
101
102 /* Port C */
103 { /* conf ppar psor pdir podr pdat */
104 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
105 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
106 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */
107 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */
108 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
109 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
110 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
111 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
112 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
113 /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
114 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
wdenkeda42082003-01-17 16:27:01 +0000[diff] [blame]115 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */
116 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */
117 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]118 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
119 /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
120 /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
121 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */
122 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
123 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */
124 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */
125 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */
126 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */
127 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */
128 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
129 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
130 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
131 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
132 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
133 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */
134 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */
135 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */
136 },
137
138 /* Port D */
139 { /* conf ppar psor pdir podr pdat */
140 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
141 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */
142 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
143 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
144 /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
145 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
146 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
147 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
148 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */
149 /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */
150 /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */
151 /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */
152 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
153 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
154 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
155 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100[diff] [blame]156#if defined(CONFIG_SYS_I2C_SOFT)
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]157 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
158 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
159#else
160#if defined(CONFIG_HARD_I2C)
161 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
162 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
163#else /* normal I/O port pins */
164 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
165 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
166#endif
167#endif
168 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
169 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
170 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
171 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
172 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */
173 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */
174 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
175 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
176 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
177 /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
178 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
179 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
180 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
181 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
182 }
183};
184
185/* ------------------------------------------------------------------------- */
186
187/* Check Board Identity:
188 */
189int checkboard (void)
190{
191 puts ("Board: PM826\n");
192 return 0;
193}
194
195/* ------------------------------------------------------------------------- */
196
197
198/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
199 *
200 * This routine performs standard 8260 initialization sequence
201 * and calculates the available memory size. It may be called
202 * several times to try different SDRAM configurations on both
203 * 60x and local buses.
204 */
205static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
206 ulong orx, volatile uchar * base)
207{
208 volatile uchar c = 0xff;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]209 volatile uint *sdmr_ptr;
210 volatile uint *orx_ptr;
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]211 ulong maxsize, size;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]212 int i;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]213
214 /* We must be able to test a location outsize the maximum legal size
215 * to find out THAT we are outside; but this address still has to be
216 * mapped by the controller. That means, that the initial mapping has
217 * to be (at least) twice as large as the maximum expected size.
218 */
219 maxsize = (1 + (~orx | 0x7fff)) / 2;
220
221 sdmr_ptr = &memctl->memc_psdmr;
222 orx_ptr = &memctl->memc_or2;
223
224 *orx_ptr = orx;
225
226 /*
227 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
228 *
229 * "At system reset, initialization software must set up the
230 * programmable parameters in the memory controller banks registers
231 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
232 * system software should execute the following initialization sequence
233 * for each SDRAM device.
234 *
235 * 1. Issue a PRECHARGE-ALL-BANKS command
236 * 2. Issue eight CBR REFRESH commands
237 * 3. Issue a MODE-SET command to initialize the mode register
238 *
239 * The initial commands are executed by setting P/LSDMR[OP] and
240 * accessing the SDRAM with a single-byte transaction."
241 *
242 * The appropriate BRx/ORx registers have already been set when we
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]243 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]244 */
245
246 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
247 *base = c;
248
249 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
250 for (i = 0; i < 8; i++)
251 *base = c;
252
253 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]254 *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]255
256 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
257 *base = c;
258
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]259 size = get_ram_size((long *)base, maxsize);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]260
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]261 *orx_ptr = orx | ~(size - 1);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]262
wdenk87249ba2004-01-06 22:38:14 +0000[diff] [blame]263 return (size);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]264}
265
266
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]267phys_size_t initdram (int board_type)
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]268{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]269 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]270 volatile memctl8260_t *memctl = &immap->im_memctl;
271
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]272#ifndef CONFIG_SYS_RAMBOOT
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]273 ulong size8, size9;
274#endif
275 ulong psize = 32 * 1024 * 1024;
276
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]277 memctl->memc_psrt = CONFIG_SYS_PSRT;
278 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]279
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]280#ifndef CONFIG_SYS_RAMBOOT
281 size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
282 (uchar *) CONFIG_SYS_SDRAM_BASE);
283 size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
284 (uchar *) CONFIG_SYS_SDRAM_BASE);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]285
286 if (size8 < size9) {
287 psize = size9;
288 printf ("(60x:9COL) ");
289 } else {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]290 psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
291 (uchar *) CONFIG_SYS_SDRAM_BASE);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]292 printf ("(60x:8COL) ");
293 }
294#endif
295 return (psize);
296}
297
Jon Loeliger145318c2007-07-09 18:38:39 -0500[diff] [blame]298#if defined(CONFIG_CMD_DOC)
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]299void doc_init (void)
300{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]301 doc_probe (CONFIG_SYS_DOC_BASE);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]302}
303#endif
wdenk28536032003-03-25 16:50:56 +0000[diff] [blame]304
wdenk1adff3d2003-03-26 11:42:53 +0000[diff] [blame]305#ifdef CONFIG_PCI
wdenk28536032003-03-25 16:50:56 +0000[diff] [blame]306struct pci_controller hose;
307
308extern void pci_mpc8250_init(struct pci_controller *);
309
310void pci_init_board(void)
311{
312 pci_mpc8250_init(&hose);
313}
wdenk1adff3d2003-03-26 11:42:53 +0000[diff] [blame]314#endif
Ben Warren052a5ea2008-08-31 20:37:00 -0700[diff] [blame]315
316int board_eth_init(bd_t *bis)
317{
318 return pci_eth_init(bis);
319}