Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2019 Toradex |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 8 | #include <init.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 9 | #include <asm/global_data.h> |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 10 | |
| 11 | #include <asm/arch/clock.h> |
| 12 | #include <asm/arch/imx8-pins.h> |
| 13 | #include <asm/arch/iomux.h> |
| 14 | #include <asm/arch/sci/sci.h> |
| 15 | #include <asm/arch/sys_proto.h> |
| 16 | #include <asm/gpio.h> |
| 17 | #include <asm/io.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 18 | #include <env.h> |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 19 | #include <errno.h> |
| 20 | #include <linux/libfdt.h> |
Philippe Schenker | 0e2980d | 2022-05-09 18:58:16 +0200 | [diff] [blame^] | 21 | #include <linux/bitops.h> |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 22 | |
| 23 | #include "../common/tdx-cfg-block.h" |
| 24 | |
| 25 | DECLARE_GLOBAL_DATA_PTR; |
| 26 | |
| 27 | #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ |
| 28 | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ |
| 29 | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ |
| 30 | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) |
| 31 | |
Philippe Schenker | 0e2980d | 2022-05-09 18:58:16 +0200 | [diff] [blame^] | 32 | #define TDX_USER_FUSE_BLOCK1_A 276 |
| 33 | #define TDX_USER_FUSE_BLOCK1_B 277 |
| 34 | #define TDX_USER_FUSE_BLOCK2_A 278 |
| 35 | #define TDX_USER_FUSE_BLOCK2_B 279 |
| 36 | |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 37 | static iomux_cfg_t uart1_pads[] = { |
| 38 | SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 39 | SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 40 | }; |
| 41 | |
Philippe Schenker | 0e2980d | 2022-05-09 18:58:16 +0200 | [diff] [blame^] | 42 | struct tdx_user_fuses { |
| 43 | u16 pid4; |
| 44 | u16 vers; |
| 45 | u8 ramid; |
| 46 | }; |
| 47 | |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 48 | static void setup_iomux_uart(void) |
| 49 | { |
| 50 | imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 51 | } |
| 52 | |
Philippe Schenker | 0e2980d | 2022-05-09 18:58:16 +0200 | [diff] [blame^] | 53 | static uint32_t do_get_tdx_user_fuse(int a, int b) |
| 54 | { |
| 55 | sc_err_t sciErr; |
| 56 | u32 val_a = 0; |
| 57 | u32 val_b = 0; |
| 58 | |
| 59 | sciErr = sc_misc_otp_fuse_read(-1, a, &val_a); |
| 60 | if (sciErr != SC_ERR_NONE) { |
| 61 | printf("Error reading out user fuse %d\n", a); |
| 62 | return 0; |
| 63 | } |
| 64 | |
| 65 | sciErr = sc_misc_otp_fuse_read(-1, b, &val_b); |
| 66 | if (sciErr != SC_ERR_NONE) { |
| 67 | printf("Error reading out user fuse %d\n", b); |
| 68 | return 0; |
| 69 | } |
| 70 | |
| 71 | return ((val_a & 0xffff) << 16) | (val_b & 0xffff); |
| 72 | } |
| 73 | |
| 74 | static void get_tdx_user_fuse(struct tdx_user_fuses *tdxuserfuse) |
| 75 | { |
| 76 | u32 fuse_block; |
| 77 | |
| 78 | fuse_block = do_get_tdx_user_fuse(TDX_USER_FUSE_BLOCK2_A, |
| 79 | TDX_USER_FUSE_BLOCK2_B); |
| 80 | |
| 81 | /* |
| 82 | * Fuse block 2 acts as a backup area, if this reads 0 we want to |
| 83 | * use fuse block 1 |
| 84 | */ |
| 85 | if (fuse_block == 0) |
| 86 | fuse_block = do_get_tdx_user_fuse(TDX_USER_FUSE_BLOCK1_A, |
| 87 | TDX_USER_FUSE_BLOCK1_B); |
| 88 | |
| 89 | tdxuserfuse->pid4 = (fuse_block >> 18) & GENMASK(13, 0); |
| 90 | tdxuserfuse->vers = (fuse_block >> 4) & GENMASK(13, 0); |
| 91 | tdxuserfuse->ramid = fuse_block & GENMASK(3, 0); |
| 92 | } |
| 93 | |
Igor Opaniuk | 96b90ba | 2020-10-22 11:21:41 +0300 | [diff] [blame] | 94 | void board_mem_get_layout(u64 *phys_sdram_1_start, |
| 95 | u64 *phys_sdram_1_size, |
| 96 | u64 *phys_sdram_2_start, |
| 97 | u64 *phys_sdram_2_size) |
| 98 | { |
| 99 | u32 is_quadplus = 0, val = 0; |
Philippe Schenker | 0e2980d | 2022-05-09 18:58:16 +0200 | [diff] [blame^] | 100 | struct tdx_user_fuses tdxramfuses; |
Igor Opaniuk | 96b90ba | 2020-10-22 11:21:41 +0300 | [diff] [blame] | 101 | sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); |
| 102 | |
| 103 | if (scierr == SC_ERR_NONE) { |
| 104 | /* QP has one A72 core disabled */ |
| 105 | is_quadplus = ((val >> 4) & 0x3) != 0x0; |
| 106 | } |
| 107 | |
Philippe Schenker | 0e2980d | 2022-05-09 18:58:16 +0200 | [diff] [blame^] | 108 | get_tdx_user_fuse(&tdxramfuses); |
| 109 | |
Igor Opaniuk | 96b90ba | 2020-10-22 11:21:41 +0300 | [diff] [blame] | 110 | *phys_sdram_1_start = PHYS_SDRAM_1; |
| 111 | *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; |
| 112 | *phys_sdram_2_start = PHYS_SDRAM_2; |
Philippe Schenker | 0e2980d | 2022-05-09 18:58:16 +0200 | [diff] [blame^] | 113 | |
| 114 | switch (tdxramfuses.ramid) { |
| 115 | case 1: |
| 116 | *phys_sdram_2_size = SZ_2G; |
| 117 | break; |
| 118 | case 2: |
Igor Opaniuk | 96b90ba | 2020-10-22 11:21:41 +0300 | [diff] [blame] | 119 | *phys_sdram_2_size = 0x0UL; |
Philippe Schenker | 0e2980d | 2022-05-09 18:58:16 +0200 | [diff] [blame^] | 120 | break; |
| 121 | case 3: |
| 122 | *phys_sdram_2_size = SZ_2G; |
| 123 | break; |
| 124 | case 4: |
| 125 | *phys_sdram_2_size = SZ_4G + SZ_2G; |
| 126 | break; |
| 127 | default: |
| 128 | if (is_quadplus) |
| 129 | /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */ |
| 130 | *phys_sdram_2_size = 0x0UL; |
| 131 | else |
| 132 | *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; |
| 133 | break; |
| 134 | } |
Igor Opaniuk | 96b90ba | 2020-10-22 11:21:41 +0300 | [diff] [blame] | 135 | } |
| 136 | |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 137 | int board_early_init_f(void) |
| 138 | { |
Anatolij Gustschin | ef156d2 | 2019-06-12 13:35:25 +0200 | [diff] [blame] | 139 | sc_pm_clock_rate_t rate = SC_80MHZ; |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 140 | sc_err_t err = 0; |
| 141 | |
Anatolij Gustschin | ef156d2 | 2019-06-12 13:35:25 +0200 | [diff] [blame] | 142 | /* Set UART1 clock root to 80 MHz and enable it */ |
| 143 | err = sc_pm_setup_uart(SC_R_UART_1, rate); |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 144 | if (err != SC_ERR_NONE) |
| 145 | return 0; |
| 146 | |
| 147 | setup_iomux_uart(); |
| 148 | |
| 149 | return 0; |
| 150 | } |
| 151 | |
Simon Glass | fa4689a | 2019-12-06 21:41:35 -0700 | [diff] [blame] | 152 | #if CONFIG_IS_ENABLED(DM_GPIO) |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 153 | static void board_gpio_init(void) |
| 154 | { |
| 155 | /* TODO */ |
| 156 | } |
| 157 | #else |
| 158 | static inline void board_gpio_init(void) {} |
| 159 | #endif |
| 160 | |
| 161 | #if IS_ENABLED(CONFIG_FEC_MXC) |
| 162 | #include <miiphy.h> |
| 163 | |
| 164 | int board_phy_config(struct phy_device *phydev) |
| 165 | { |
| 166 | if (phydev->drv->config) |
| 167 | phydev->drv->config(phydev); |
| 168 | |
| 169 | return 0; |
| 170 | } |
| 171 | #endif |
| 172 | |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 173 | int checkboard(void) |
| 174 | { |
| 175 | puts("Model: Toradex Apalis iMX8\n"); |
| 176 | |
| 177 | build_info(); |
| 178 | print_bootinfo(); |
| 179 | |
| 180 | return 0; |
| 181 | } |
| 182 | |
| 183 | int board_init(void) |
| 184 | { |
| 185 | board_gpio_init(); |
| 186 | |
| 187 | return 0; |
| 188 | } |
| 189 | |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 190 | /* |
| 191 | * Board specific reset that is system reset. |
| 192 | */ |
Harald Seiler | 6f14d5f | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 193 | void reset_cpu(void) |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 194 | { |
| 195 | /* TODO */ |
| 196 | } |
| 197 | |
| 198 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 199 | int ft_board_setup(void *blob, struct bd_info *bd) |
Marcel Ziswiler | 475ceff | 2019-05-31 19:00:20 +0300 | [diff] [blame] | 200 | { |
| 201 | return ft_common_board_setup(blob, bd); |
| 202 | } |
| 203 | #endif |
| 204 | |
| 205 | int board_mmc_get_env_dev(int devno) |
| 206 | { |
| 207 | return devno; |
| 208 | } |
| 209 | |
| 210 | int board_late_init(void) |
| 211 | { |
| 212 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 213 | /* TODO move to common */ |
| 214 | env_set("board_name", "Apalis iMX8QM"); |
| 215 | env_set("board_rev", "v1.0"); |
| 216 | #endif |
| 217 | |
| 218 | return 0; |
| 219 | } |