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git01.mediatek.com / filogic / uboot / 0e00310afba05430fbb73a3a25f50346db4f066c / . / arch / arm / dts / rk3568-rock-3a-u-boot.dtsi
blob: 29c18f5a340a51134dcdc922ebdb067d61b9ea1b [file] [log] [blame]
Akash Gajjara01866a2023-02-14 20:48:40 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 * (C) Copyright 2023 Akash Gajjar <gajjar04akash@gmail.com>
5 */
6
7#include "rk356x-u-boot.dtsi"
8
FUKAUMI Naokiabe667d2024-08-09 07:23:25 +0900[diff] [blame]9/ {
10 leds {
11 led-0 {
12 default-state = "on";
13 };
14 };
15};
16
Jonas Karlman1e1bc892023-07-22 13:30:23 +0000[diff] [blame]17&pcie3x2 {
Jonas Karlmandd7ee8a2023-07-31 04:28:34 +0000[diff] [blame]18 pinctrl-0 = <&pcie3x2_reset_h>;
Jonas Karlman1e1bc892023-07-22 13:30:23 +0000[diff] [blame]19};
20
Jonas Karlmanac46dc72023-05-17 18:26:34 +0000[diff] [blame]21&pinctrl {
Jonas Karlman1e1bc892023-07-22 13:30:23 +0000[diff] [blame]22 pcie {
23 pcie3x2_reset_h: pcie3x2-reset-h {
24 rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
25 };
26 };
Jonas Karlmanac46dc72023-05-17 18:26:34 +0000[diff] [blame]27};
28
Jonas Karlman2cc03212023-04-18 16:46:38 +0000[diff] [blame]29&sdhci {
30 cap-mmc-highspeed;
Jonas Karlman2cc03212023-04-18 16:46:38 +0000[diff] [blame]31 mmc-hs200-1_8v;
32 mmc-hs400-1_8v;
33 mmc-hs400-enhanced-strobe;
34};
35
Jonas Karlmana9d8d532023-05-17 18:26:35 +0000[diff] [blame]36&sfc {
Jonas Karlmana9d8d532023-05-17 18:26:35 +0000[diff] [blame]37 flash@0 {
Jonas Karlmandc3daaa2024-04-22 06:28:49 +0000[diff] [blame]38 bootph-pre-ram;
39 bootph-some-ram;
Jonas Karlmana9d8d532023-05-17 18:26:35 +0000[diff] [blame]40 };
41};
FUKAUMI Naoki4604cbe2024-08-02 11:49:49 +0900[diff] [blame]42
43&usb_host0_ohci {
44 status = "disabled";
45};