| developer | 13dc3c8 | 2020-10-16 11:38:39 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions |
| 4 | * |
| 5 | * Copyright (C) 2016 MediaTek Inc. |
| 6 | * |
| 7 | * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> |
| 8 | */ |
| 9 | |
| 10 | #ifndef _SSUSB_HW_REGS_H_ |
| 11 | #define _SSUSB_HW_REGS_H_ |
| 12 | |
| 13 | /* segment offset of MAC register */ |
| 14 | #define SSUSB_XCHI_BASE 0x0000 |
| 15 | #define SSUSB_DEV_BASE 0x1000 |
| 16 | #define SSUSB_EPCTL_CSR_BASE 0x1800 |
| 17 | #define SSUSB_USB3_MAC_CSR_BASE 0x2400 |
| 18 | #define SSUSB_USB3_SYS_CSR_BASE 0x2400 |
| 19 | #define SSUSB_USB2_CSR_BASE 0x3400 |
| 20 | |
| 21 | /* IPPC register in Infra */ |
| 22 | #define SSUSB_SIFSLV_IPPC_BASE 0x0000 |
| 23 | |
| 24 | /* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */ |
| 25 | |
| 26 | #define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000) |
| 27 | #define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004) |
| 28 | #define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008) |
| 29 | #define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C) |
| 30 | |
| 31 | #define U3D_EPISR (SSUSB_DEV_BASE + 0x0080) |
| 32 | #define U3D_EPIER (SSUSB_DEV_BASE + 0x0084) |
| 33 | #define U3D_EPIESR (SSUSB_DEV_BASE + 0x0088) |
| 34 | #define U3D_EPIECR (SSUSB_DEV_BASE + 0x008C) |
| 35 | |
| 36 | #define U3D_EP0CSR (SSUSB_DEV_BASE + 0x0100) |
| 37 | #define U3D_RXCOUNT0 (SSUSB_DEV_BASE + 0x0108) |
| 38 | #define U3D_RESERVED (SSUSB_DEV_BASE + 0x010C) |
| 39 | #define U3D_TX1CSR0 (SSUSB_DEV_BASE + 0x0110) |
| 40 | #define U3D_TX1CSR1 (SSUSB_DEV_BASE + 0x0114) |
| 41 | #define U3D_TX1CSR2 (SSUSB_DEV_BASE + 0x0118) |
| 42 | |
| 43 | #define U3D_RX1CSR0 (SSUSB_DEV_BASE + 0x0210) |
| 44 | #define U3D_RX1CSR1 (SSUSB_DEV_BASE + 0x0214) |
| 45 | #define U3D_RX1CSR2 (SSUSB_DEV_BASE + 0x0218) |
| 46 | |
| 47 | #define U3D_FIFO0 (SSUSB_DEV_BASE + 0x0300) |
| 48 | |
| 49 | #define U3D_QCR0 (SSUSB_DEV_BASE + 0x0400) |
| 50 | #define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404) |
| 51 | #define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408) |
| 52 | #define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C) |
| 53 | #define U3D_QFCR (SSUSB_DEV_BASE + 0x0428) |
| 54 | |
| 55 | #define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510) |
| 56 | #define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514) |
| 57 | #define U3D_TXQCPR1 (SSUSB_DEV_BASE + 0x0518) |
| 58 | |
| 59 | #define U3D_RXQCSR1 (SSUSB_DEV_BASE + 0x0610) |
| 60 | #define U3D_RXQSAR1 (SSUSB_DEV_BASE + 0x0614) |
| 61 | #define U3D_RXQCPR1 (SSUSB_DEV_BASE + 0x0618) |
| 62 | #define U3D_RXQLDPR1 (SSUSB_DEV_BASE + 0x061C) |
| 63 | |
| 64 | #define U3D_QISAR0 (SSUSB_DEV_BASE + 0x0700) |
| 65 | #define U3D_QIER0 (SSUSB_DEV_BASE + 0x0704) |
| 66 | #define U3D_QIESR0 (SSUSB_DEV_BASE + 0x0708) |
| 67 | #define U3D_QIECR0 (SSUSB_DEV_BASE + 0x070C) |
| 68 | #define U3D_QISAR1 (SSUSB_DEV_BASE + 0x0710) |
| 69 | #define U3D_QIER1 (SSUSB_DEV_BASE + 0x0714) |
| 70 | #define U3D_QIESR1 (SSUSB_DEV_BASE + 0x0718) |
| 71 | #define U3D_QIECR1 (SSUSB_DEV_BASE + 0x071C) |
| 72 | |
| 73 | #define U3D_TQERRIR0 (SSUSB_DEV_BASE + 0x0780) |
| 74 | #define U3D_TQERRIER0 (SSUSB_DEV_BASE + 0x0784) |
| 75 | #define U3D_TQERRIESR0 (SSUSB_DEV_BASE + 0x0788) |
| 76 | #define U3D_TQERRIECR0 (SSUSB_DEV_BASE + 0x078C) |
| 77 | #define U3D_RQERRIR0 (SSUSB_DEV_BASE + 0x07C0) |
| 78 | #define U3D_RQERRIER0 (SSUSB_DEV_BASE + 0x07C4) |
| 79 | #define U3D_RQERRIESR0 (SSUSB_DEV_BASE + 0x07C8) |
| 80 | #define U3D_RQERRIECR0 (SSUSB_DEV_BASE + 0x07CC) |
| 81 | #define U3D_RQERRIR1 (SSUSB_DEV_BASE + 0x07D0) |
| 82 | #define U3D_RQERRIER1 (SSUSB_DEV_BASE + 0x07D4) |
| 83 | #define U3D_RQERRIESR1 (SSUSB_DEV_BASE + 0x07D8) |
| 84 | #define U3D_RQERRIECR1 (SSUSB_DEV_BASE + 0x07DC) |
| 85 | |
| 86 | #define U3D_CAP_EP0FFSZ (SSUSB_DEV_BASE + 0x0C04) |
| 87 | #define U3D_CAP_EPNTXFFSZ (SSUSB_DEV_BASE + 0x0C08) |
| 88 | #define U3D_CAP_EPNRXFFSZ (SSUSB_DEV_BASE + 0x0C0C) |
| 89 | #define U3D_CAP_EPINFO (SSUSB_DEV_BASE + 0x0C10) |
| 90 | #define U3D_MISC_CTRL (SSUSB_DEV_BASE + 0x0C84) |
| 91 | |
| 92 | /*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/ |
| 93 | |
| 94 | /* U3D_LV1ISR */ |
| 95 | #define EP_CTRL_INTR BIT(5) |
| 96 | #define MAC2_INTR BIT(4) |
| 97 | #define DMA_INTR BIT(3) |
| 98 | #define MAC3_INTR BIT(2) |
| 99 | #define QMU_INTR BIT(1) |
| 100 | #define BMU_INTR BIT(0) |
| 101 | |
| 102 | /* U3D_LV1IECR */ |
| 103 | #define LV1IECR_MSK GENMASK(31, 0) |
| 104 | |
| 105 | /* U3D_EPISR */ |
| 106 | #define EPRISR(x) (BIT(16) << (x)) |
| 107 | #define SETUPENDISR BIT(16) |
| 108 | #define EPTISR(x) (BIT(0) << (x)) |
| 109 | #define EP0ISR BIT(0) |
| 110 | |
| 111 | /* U3D_EP0CSR */ |
| 112 | #define EP0_SENDSTALL BIT(25) |
| 113 | #define EP0_FIFOFULL BIT(23) |
| 114 | #define EP0_SENTSTALL BIT(22) |
| 115 | #define EP0_DPHTX BIT(20) |
| 116 | #define EP0_DATAEND BIT(19) |
| 117 | #define EP0_TXPKTRDY BIT(18) |
| 118 | #define EP0_SETUPPKTRDY BIT(17) |
| 119 | #define EP0_RXPKTRDY BIT(16) |
| 120 | #define EP0_MAXPKTSZ_MSK GENMASK(9, 0) |
| 121 | #define EP0_MAXPKTSZ(x) ((x) & EP0_MAXPKTSZ_MSK) |
| 122 | #define EP0_W1C_BITS (~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL)) |
| 123 | |
| 124 | /* U3D_TX1CSR0 */ |
| 125 | #define TX_DMAREQEN BIT(29) |
| 126 | #define TX_FIFOFULL BIT(25) |
| 127 | #define TX_FIFOEMPTY BIT(24) |
| 128 | #define TX_SENTSTALL BIT(22) |
| 129 | #define TX_SENDSTALL BIT(21) |
| 130 | #define TX_TXPKTRDY BIT(16) |
| 131 | #define TX_TXMAXPKTSZ_MSK GENMASK(10, 0) |
| 132 | #define TX_TXMAXPKTSZ(x) ((x) & TX_TXMAXPKTSZ_MSK) |
| 133 | #define TX_W1C_BITS (~(TX_SENTSTALL)) |
| 134 | |
| 135 | /* U3D_TX1CSR1 */ |
| 136 | #define TX_MAX_PKT_G2(x) (((x) & 0xff) << 24) |
| 137 | #define TX_MULT_G2(x) (((x) & 0x7) << 21) |
| 138 | #define TX_MULT_OG(x) (((x) & 0x3) << 22) |
| 139 | #define TX_MAX_PKT_OG(x) (((x) & 0x3f) << 16) |
| 140 | #define TX_SLOT(x) (((x) & 0x3f) << 8) |
| 141 | #define TX_TYPE(x) (((x) & 0x3) << 4) |
| 142 | #define TX_SS_BURST(x) (((x) & 0xf) << 0) |
| 143 | #define TX_MULT(g2c, x) \ |
| 144 | ({ \ |
| 145 | typeof(x) x_ = (x); \ |
| 146 | (g2c) ? TX_MULT_G2(x_) : TX_MULT_OG(x_); \ |
| 147 | }) |
| 148 | #define TX_MAX_PKT(g2c, x) \ |
| 149 | ({ \ |
| 150 | typeof(x) x_ = (x); \ |
| 151 | (g2c) ? TX_MAX_PKT_G2(x_) : TX_MAX_PKT_OG(x_); \ |
| 152 | }) |
| 153 | |
| 154 | /* for TX_TYPE & RX_TYPE */ |
| 155 | #define TYPE_BULK (0x0) |
| 156 | #define TYPE_INT (0x1) |
| 157 | #define TYPE_ISO (0x2) |
| 158 | #define TYPE_MASK (0x3) |
| 159 | |
| 160 | /* U3D_TX1CSR2 */ |
| 161 | #define TX_BINTERVAL(x) (((x) & 0xff) << 24) |
| 162 | #define TX_FIFOSEGSIZE(x) (((x) & 0xf) << 16) |
| 163 | #define TX_FIFOADDR(x) (((x) & 0x1fff) << 0) |
| 164 | |
| 165 | /* U3D_RX1CSR0 */ |
| 166 | #define RX_DMAREQEN BIT(29) |
| 167 | #define RX_SENTSTALL BIT(22) |
| 168 | #define RX_SENDSTALL BIT(21) |
| 169 | #define RX_RXPKTRDY BIT(16) |
| 170 | #define RX_RXMAXPKTSZ_MSK GENMASK(10, 0) |
| 171 | #define RX_RXMAXPKTSZ(x) ((x) & RX_RXMAXPKTSZ_MSK) |
| 172 | #define RX_W1C_BITS (~(RX_SENTSTALL | RX_RXPKTRDY)) |
| 173 | |
| 174 | /* U3D_RX1CSR1 */ |
| 175 | #define RX_MAX_PKT_G2(x) (((x) & 0xff) << 24) |
| 176 | #define RX_MULT_G2(x) (((x) & 0x7) << 21) |
| 177 | #define RX_MULT_OG(x) (((x) & 0x3) << 22) |
| 178 | #define RX_MAX_PKT_OG(x) (((x) & 0x3f) << 16) |
| 179 | #define RX_SLOT(x) (((x) & 0x3f) << 8) |
| 180 | #define RX_TYPE(x) (((x) & 0x3) << 4) |
| 181 | #define RX_SS_BURST(x) (((x) & 0xf) << 0) |
| 182 | #define RX_MULT(g2c, x) \ |
| 183 | ({ \ |
| 184 | typeof(x) x_ = (x); \ |
| 185 | (g2c) ? RX_MULT_G2(x_) : RX_MULT_OG(x_); \ |
| 186 | }) |
| 187 | #define RX_MAX_PKT(g2c, x) \ |
| 188 | ({ \ |
| 189 | typeof(x) x_ = (x); \ |
| 190 | (g2c) ? RX_MAX_PKT_G2(x_) : RX_MAX_PKT_OG(x_); \ |
| 191 | }) |
| 192 | |
| 193 | /* U3D_RX1CSR2 */ |
| 194 | #define RX_BINTERVAL(x) (((x) & 0xff) << 24) |
| 195 | #define RX_FIFOSEGSIZE(x) (((x) & 0xf) << 16) |
| 196 | #define RX_FIFOADDR(x) (((x) & 0x1fff) << 0) |
| 197 | |
| 198 | /* U3D_QCR0 */ |
| 199 | #define QMU_RX_CS_EN(x) (BIT(16) << (x)) |
| 200 | #define QMU_TX_CS_EN(x) (BIT(0) << (x)) |
| 201 | #define QMU_CS16B_EN BIT(0) |
| 202 | |
| 203 | /* U3D_QCR1 */ |
| 204 | #define QMU_TX_ZLP(x) (BIT(0) << (x)) |
| 205 | |
| 206 | /* U3D_QCR3 */ |
| 207 | #define QMU_RX_COZ(x) (BIT(16) << (x)) |
| 208 | #define QMU_RX_ZLP(x) (BIT(0) << (x)) |
| 209 | |
| 210 | /* U3D_TXQCSR1 */ |
| 211 | /* U3D_RXQCSR1 */ |
| 212 | #define QMU_Q_ACTIVE BIT(15) |
| 213 | #define QMU_Q_STOP BIT(2) |
| 214 | #define QMU_Q_RESUME BIT(1) |
| 215 | #define QMU_Q_START BIT(0) |
| 216 | |
| 217 | /* U3D_QISAR0, U3D_QIER0, U3D_QIESR0, U3D_QIECR0 */ |
| 218 | #define QMU_RX_DONE_INT(x) (BIT(16) << (x)) |
| 219 | #define QMU_TX_DONE_INT(x) (BIT(0) << (x)) |
| 220 | |
| 221 | /* U3D_QISAR1, U3D_QIER1, U3D_QIESR1, U3D_QIECR1 */ |
| 222 | #define RXQ_ZLPERR_INT BIT(20) |
| 223 | #define RXQ_LENERR_INT BIT(18) |
| 224 | #define RXQ_CSERR_INT BIT(17) |
| 225 | #define RXQ_EMPTY_INT BIT(16) |
| 226 | #define TXQ_LENERR_INT BIT(2) |
| 227 | #define TXQ_CSERR_INT BIT(1) |
| 228 | #define TXQ_EMPTY_INT BIT(0) |
| 229 | |
| 230 | /* U3D_TQERRIR0, U3D_TQERRIER0, U3D_TQERRIESR0, U3D_TQERRIECR0 */ |
| 231 | #define QMU_TX_LEN_ERR(x) (BIT(16) << (x)) |
| 232 | #define QMU_TX_CS_ERR(x) (BIT(0) << (x)) |
| 233 | |
| 234 | /* U3D_RQERRIR0, U3D_RQERRIER0, U3D_RQERRIESR0, U3D_RQERRIECR0 */ |
| 235 | #define QMU_RX_LEN_ERR(x) (BIT(16) << (x)) |
| 236 | #define QMU_RX_CS_ERR(x) (BIT(0) << (x)) |
| 237 | |
| 238 | /* U3D_RQERRIR1, U3D_RQERRIER1, U3D_RQERRIESR1, U3D_RQERRIECR1 */ |
| 239 | #define QMU_RX_ZLP_ERR(n) (BIT(16) << (n)) |
| 240 | |
| 241 | /* U3D_CAP_EPINFO */ |
| 242 | #define CAP_RX_EP_NUM(x) (((x) >> 8) & 0x1f) |
| 243 | #define CAP_TX_EP_NUM(x) ((x) & 0x1f) |
| 244 | |
| 245 | /* U3D_MISC_CTRL */ |
| 246 | #define VBUS_ON BIT(1) |
| 247 | #define VBUS_FRC_EN BIT(0) |
| 248 | |
| 249 | /*---------------- SSUSB_EPCTL_CSR REGISTER DEFINITION ----------------*/ |
| 250 | |
| 251 | #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000) |
| 252 | #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004) |
| 253 | |
| 254 | #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050) |
| 255 | #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054) |
| 256 | |
| 257 | /*---------------- SSUSB_EPCTL_CSR FIELD DEFINITION ----------------*/ |
| 258 | |
| 259 | /* U3D_DEVICE_CONF */ |
| 260 | #define DEV_ADDR_MSK GENMASK(30, 24) |
| 261 | #define DEV_ADDR(x) ((0x7f & (x)) << 24) |
| 262 | #define HW_USB2_3_SEL BIT(18) |
| 263 | #define SW_USB2_3_SEL_EN BIT(17) |
| 264 | #define SW_USB2_3_SEL BIT(16) |
| 265 | #define SSUSB_DEV_SPEED(x) ((x) & 0x7) |
| 266 | |
| 267 | /* U3D_EP_RST */ |
| 268 | #define EP1_IN_RST BIT(17) |
| 269 | #define EP1_OUT_RST BIT(1) |
| 270 | #define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum)) |
| 271 | #define EP0_RST BIT(0) |
| 272 | |
| 273 | /* U3D_DEV_LINK_INTR_ENABLE */ |
| 274 | /* U3D_DEV_LINK_INTR */ |
| 275 | #define SSUSB_DEV_SPEED_CHG_INTR BIT(0) |
| 276 | |
| 277 | /*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/ |
| 278 | |
| 279 | #define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0010) |
| 280 | #define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE + 0x001C) |
| 281 | |
| 282 | #define U3D_LINK_STATE_MACHINE (SSUSB_USB3_MAC_CSR_BASE + 0x0134) |
| 283 | #define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C) |
| 284 | #define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140) |
| 285 | |
| 286 | #define U3D_U3U2_SWITCH_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0170) |
| 287 | |
| 288 | /*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/ |
| 289 | |
| 290 | /* U3D_LTSSM_CTRL */ |
| 291 | #define FORCE_POLLING_FAIL BIT(4) |
| 292 | #define FORCE_RXDETECT_FAIL BIT(3) |
| 293 | #define SOFT_U3_EXIT_EN BIT(2) |
| 294 | #define COMPLIANCE_EN BIT(1) |
| 295 | #define U1_GO_U2_EN BIT(0) |
| 296 | |
| 297 | /* U3D_USB3_CONFIG */ |
| 298 | #define USB3_EN BIT(0) |
| 299 | |
| 300 | /* U3D_LINK_STATE_MACHINE */ |
| 301 | #define LTSSM_STATE(x) ((x) & 0x1f) |
| 302 | |
| 303 | /* U3D_LTSSM_INTR_ENABLE */ |
| 304 | /* U3D_LTSSM_INTR */ |
| 305 | #define U3_RESUME_INTR BIT(18) |
| 306 | #define U3_LFPS_TMOUT_INTR BIT(17) |
| 307 | #define VBUS_FALL_INTR BIT(16) |
| 308 | #define VBUS_RISE_INTR BIT(15) |
| 309 | #define RXDET_SUCCESS_INTR BIT(14) |
| 310 | #define EXIT_U3_INTR BIT(13) |
| 311 | #define EXIT_U2_INTR BIT(12) |
| 312 | #define EXIT_U1_INTR BIT(11) |
| 313 | #define ENTER_U3_INTR BIT(10) |
| 314 | #define ENTER_U2_INTR BIT(9) |
| 315 | #define ENTER_U1_INTR BIT(8) |
| 316 | #define ENTER_U0_INTR BIT(7) |
| 317 | #define RECOVERY_INTR BIT(6) |
| 318 | #define WARM_RST_INTR BIT(5) |
| 319 | #define HOT_RST_INTR BIT(4) |
| 320 | #define LOOPBACK_INTR BIT(3) |
| 321 | #define COMPLIANCE_INTR BIT(2) |
| 322 | #define SS_DISABLE_INTR BIT(1) |
| 323 | #define SS_INACTIVE_INTR BIT(0) |
| 324 | |
| 325 | /* U3D_U3U2_SWITCH_CTRL */ |
| 326 | #define SOFTCON_CLR_AUTO_EN BIT(0) |
| 327 | |
| 328 | /*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/ |
| 329 | |
| 330 | #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C) |
| 331 | #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210) |
| 332 | #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214) |
| 333 | |
| 334 | /*---------------- SSUSB_USB3_SYS_CSR FIELD DEFINITION ----------------*/ |
| 335 | |
| 336 | /* U3D_LINK_UX_INACT_TIMER */ |
| 337 | #define DEV_U2_INACT_TIMEOUT_MSK GENMASK(23, 16) |
| 338 | #define DEV_U2_INACT_TIMEOUT_VALUE(x) (((x) & 0xff) << 16) |
| 339 | #define U2_INACT_TIMEOUT_MSK GENMASK(15, 8) |
| 340 | #define U1_INACT_TIMEOUT_MSK GENMASK(7, 0) |
| 341 | #define U1_INACT_TIMEOUT_VALUE(x) ((x) & 0xff) |
| 342 | |
| 343 | /* U3D_LINK_POWER_CONTROL */ |
| 344 | #define SW_U2_ACCEPT_ENABLE BIT(9) |
| 345 | #define SW_U1_ACCEPT_ENABLE BIT(8) |
| 346 | #define UX_EXIT BIT(5) |
| 347 | #define LGO_U3 BIT(4) |
| 348 | #define LGO_U2 BIT(3) |
| 349 | #define LGO_U1 BIT(2) |
| 350 | #define SW_U2_REQUEST_ENABLE BIT(1) |
| 351 | #define SW_U1_REQUEST_ENABLE BIT(0) |
| 352 | |
| 353 | /* U3D_LINK_ERR_COUNT */ |
| 354 | #define CLR_LINK_ERR_CNT BIT(16) |
| 355 | #define LINK_ERROR_COUNT GENMASK(15, 0) |
| 356 | |
| 357 | /*---------------- SSUSB_USB2_CSR REGISTER DEFINITION ----------------*/ |
| 358 | |
| 359 | #define U3D_POWER_MANAGEMENT (SSUSB_USB2_CSR_BASE + 0x0004) |
| 360 | #define U3D_DEVICE_CONTROL (SSUSB_USB2_CSR_BASE + 0x000C) |
| 361 | #define U3D_USB2_TEST_MODE (SSUSB_USB2_CSR_BASE + 0x0014) |
| 362 | #define U3D_COMMON_USB_INTR_ENABLE (SSUSB_USB2_CSR_BASE + 0x0018) |
| 363 | #define U3D_COMMON_USB_INTR (SSUSB_USB2_CSR_BASE + 0x001C) |
| 364 | #define U3D_LINK_RESET_INFO (SSUSB_USB2_CSR_BASE + 0x0024) |
| 365 | #define U3D_USB20_FRAME_NUM (SSUSB_USB2_CSR_BASE + 0x003C) |
| 366 | #define U3D_USB20_LPM_PARAMETER (SSUSB_USB2_CSR_BASE + 0x0044) |
| 367 | #define U3D_USB20_MISC_CONTROL (SSUSB_USB2_CSR_BASE + 0x004C) |
| 368 | #define U3D_USB20_OPSTATE (SSUSB_USB2_CSR_BASE + 0x0060) |
| 369 | |
| 370 | /*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/ |
| 371 | |
| 372 | /* U3D_POWER_MANAGEMENT */ |
| 373 | #define LPM_BESL_STALL BIT(14) |
| 374 | #define LPM_BESLD_STALL BIT(13) |
| 375 | #define LPM_RWP BIT(11) |
| 376 | #define LPM_HRWE BIT(10) |
| 377 | #define LPM_MODE(x) (((x) & 0x3) << 8) |
| 378 | #define ISO_UPDATE BIT(7) |
| 379 | #define SOFT_CONN BIT(6) |
| 380 | #define HS_ENABLE BIT(5) |
| 381 | #define RESUME BIT(2) |
| 382 | #define SUSPENDM_ENABLE BIT(0) |
| 383 | |
| 384 | /* U3D_DEVICE_CONTROL */ |
| 385 | #define DC_HOSTREQ BIT(1) |
| 386 | #define DC_SESSION BIT(0) |
| 387 | |
| 388 | /* U3D_USB2_TEST_MODE */ |
| 389 | #define U2U3_AUTO_SWITCH BIT(10) |
| 390 | #define LPM_FORCE_STALL BIT(8) |
| 391 | #define FIFO_ACCESS BIT(6) |
| 392 | #define FORCE_FS BIT(5) |
| 393 | #define FORCE_HS BIT(4) |
| 394 | #define TEST_PACKET_MODE BIT(3) |
| 395 | #define TEST_K_MODE BIT(2) |
| 396 | #define TEST_J_MODE BIT(1) |
| 397 | #define TEST_SE0_NAK_MODE BIT(0) |
| 398 | |
| 399 | /* U3D_COMMON_USB_INTR_ENABLE */ |
| 400 | /* U3D_COMMON_USB_INTR */ |
| 401 | #define LPM_RESUME_INTR BIT(9) |
| 402 | #define LPM_INTR BIT(8) |
| 403 | #define DISCONN_INTR BIT(5) |
| 404 | #define CONN_INTR BIT(4) |
| 405 | #define SOF_INTR BIT(3) |
| 406 | #define RESET_INTR BIT(2) |
| 407 | #define RESUME_INTR BIT(1) |
| 408 | #define SUSPEND_INTR BIT(0) |
| 409 | |
| 410 | /* U3D_LINK_RESET_INFO */ |
| 411 | #define WTCHRP_MSK GENMASK(19, 16) |
| 412 | |
| 413 | /* U3D_USB20_LPM_PARAMETER */ |
| 414 | #define LPM_BESLCK_U3(x) (((x) & 0xf) << 12) |
| 415 | #define LPM_BESLCK(x) (((x) & 0xf) << 8) |
| 416 | #define LPM_BESLDCK(x) (((x) & 0xf) << 4) |
| 417 | #define LPM_BESL GENMASK(3, 0) |
| 418 | |
| 419 | /* U3D_USB20_MISC_CONTROL */ |
| 420 | #define LPM_U3_ACK_EN BIT(0) |
| 421 | |
| 422 | /*---------------- SSUSB_SIFSLV_IPPC REGISTER DEFINITION ----------------*/ |
| 423 | |
| 424 | #define U3D_SSUSB_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000) |
| 425 | #define U3D_SSUSB_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004) |
| 426 | #define U3D_SSUSB_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008) |
| 427 | #define U3D_SSUSB_IP_PW_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x000C) |
| 428 | #define U3D_SSUSB_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010) |
| 429 | #define U3D_SSUSB_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014) |
| 430 | #define U3D_SSUSB_OTG_STS (SSUSB_SIFSLV_IPPC_BASE + 0x0018) |
| 431 | #define U3D_SSUSB_OTG_STS_CLR (SSUSB_SIFSLV_IPPC_BASE + 0x001C) |
| 432 | #define U3D_SSUSB_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024) |
| 433 | #define U3D_SSUSB_IP_DEV_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0028) |
| 434 | #define U3D_SSUSB_OTG_INT_EN (SSUSB_SIFSLV_IPPC_BASE + 0x002C) |
| 435 | #define U3D_SSUSB_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030) |
| 436 | #define U3D_SSUSB_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050) |
| 437 | #define U3D_SSUSB_REF_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x008C) |
| 438 | #define U3D_SSUSB_DEV_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x0098) |
| 439 | #define U3D_SSUSB_HW_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A0) |
| 440 | #define U3D_SSUSB_HW_SUB_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A4) |
| 441 | #define U3D_SSUSB_IP_TRUNK_VERS (U3D_SSUSB_HW_SUB_ID) |
| 442 | #define U3D_SSUSB_PRB_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x00B0) |
| 443 | #define U3D_SSUSB_PRB_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x00B4) |
| 444 | #define U3D_SSUSB_PRB_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x00B8) |
| 445 | #define U3D_SSUSB_PRB_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x00BC) |
| 446 | #define U3D_SSUSB_PRB_CTRL4 (SSUSB_SIFSLV_IPPC_BASE + 0x00C0) |
| 447 | #define U3D_SSUSB_PRB_CTRL5 (SSUSB_SIFSLV_IPPC_BASE + 0x00C4) |
| 448 | #define U3D_SSUSB_IP_SPARE0 (SSUSB_SIFSLV_IPPC_BASE + 0x00C8) |
| 449 | |
| 450 | /*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/ |
| 451 | |
| 452 | /* U3D_SSUSB_IP_PW_CTRL0 */ |
| 453 | #define SSUSB_IP_SW_RST BIT(0) |
| 454 | |
| 455 | /* U3D_SSUSB_IP_PW_CTRL1 */ |
| 456 | #define SSUSB_IP_HOST_PDN BIT(0) |
| 457 | |
| 458 | /* U3D_SSUSB_IP_PW_CTRL2 */ |
| 459 | #define SSUSB_IP_DEV_PDN BIT(0) |
| 460 | |
| 461 | /* U3D_SSUSB_IP_PW_CTRL3 */ |
| 462 | #define SSUSB_IP_PCIE_PDN BIT(0) |
| 463 | |
| 464 | /* U3D_SSUSB_IP_PW_STS1 */ |
| 465 | #define SSUSB_IP_SLEEP_STS BIT(30) |
| 466 | #define SSUSB_U3_MAC_RST_B_STS BIT(16) |
| 467 | #define SSUSB_XHCI_RST_B_STS BIT(11) |
| 468 | #define SSUSB_SYS125_RST_B_STS BIT(10) |
| 469 | #define SSUSB_REF_RST_B_STS BIT(8) |
| 470 | #define SSUSB_SYSPLL_STABLE BIT(0) |
| 471 | |
| 472 | /* U3D_SSUSB_IP_PW_STS2 */ |
| 473 | #define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0) |
| 474 | |
| 475 | /* U3D_SSUSB_OTG_STS */ |
| 476 | #define SSUSB_VBUS_VALID BIT(9) |
| 477 | |
| 478 | /* U3D_SSUSB_OTG_STS_CLR */ |
| 479 | #define SSUSB_VBUS_INTR_CLR BIT(6) |
| 480 | |
| 481 | /* U3D_SSUSB_IP_XHCI_CAP */ |
| 482 | #define SSUSB_IP_XHCI_U2_PORT_NUM(x) (((x) >> 8) & 0xff) |
| 483 | #define SSUSB_IP_XHCI_U3_PORT_NUM(x) ((x) & 0xff) |
| 484 | |
| 485 | /* U3D_SSUSB_IP_DEV_CAP */ |
| 486 | #define SSUSB_IP_DEV_U3_PORT_NUM(x) ((x) & 0xff) |
| 487 | |
| 488 | /* U3D_SSUSB_OTG_INT_EN */ |
| 489 | #define SSUSB_VBUS_CHG_INT_A_EN BIT(7) |
| 490 | #define SSUSB_VBUS_CHG_INT_B_EN BIT(6) |
| 491 | |
| 492 | /* U3D_SSUSB_U3_CTRL_0P */ |
| 493 | #define SSUSB_U3_PORT_SSP_SPEED BIT(9) |
| 494 | #define SSUSB_U3_PORT_DUAL_MODE BIT(7) |
| 495 | #define SSUSB_U3_PORT_HOST_SEL BIT(2) |
| 496 | #define SSUSB_U3_PORT_PDN BIT(1) |
| 497 | #define SSUSB_U3_PORT_DIS BIT(0) |
| 498 | |
| 499 | /* U3D_SSUSB_U2_CTRL_0P */ |
| 500 | #define SSUSB_U2_PORT_RG_IDDIG BIT(12) |
| 501 | #define SSUSB_U2_PORT_FORCE_IDDIG BIT(11) |
| 502 | #define SSUSB_U2_PORT_VBUSVALID BIT(9) |
| 503 | #define SSUSB_U2_PORT_OTG_SEL BIT(7) |
| 504 | #define SSUSB_U2_PORT_HOST BIT(2) |
| 505 | #define SSUSB_U2_PORT_PDN BIT(1) |
| 506 | #define SSUSB_U2_PORT_DIS BIT(0) |
| 507 | #define SSUSB_U2_PORT_HOST_SEL (SSUSB_U2_PORT_VBUSVALID | SSUSB_U2_PORT_HOST) |
| 508 | |
| 509 | /* U3D_SSUSB_DEV_RST_CTRL */ |
| 510 | #define SSUSB_DEV_SW_RST BIT(0) |
| 511 | |
| 512 | /* U3D_SSUSB_IP_TRUNK_VERS */ |
| 513 | #define IP_TRUNK_VERS(x) (((x) >> 16) & 0xffff) |
| 514 | |
| 515 | #endif /* _SSUSB_HW_REGS_H_ */ |