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git01.mediatek.com / filogic / uboot / 0de669fbc6510b9c9669d01e678377fdd8724fa8 / . / board / mpr2 / lowlevel_init.S
blob: 5f02bd4bb26cf843e4faae587db1c23d0ab3b38b [file] [log] [blame]
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]1/*
2 * (C) Copyright 2008
3 * Mark Jonas <mark.jonas@de.bosch.com>
4 *
5 * (C) Copyright 2007
6 * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * board/mpr2/lowlevel_init.S
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]25#include <asm/macro.h>
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]26
27 .global lowlevel_init
28
29 .text
30 .align 2
31
32lowlevel_init:
33
34/*
35 * Set frequency multipliers and dividers in FRQCR.
36 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]37 write16 WTCSR_A, WTCSR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]38
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]39 write16 WTCNT_A, WTCNT_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]40
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]41 write16 FRQCR_A, FRQCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]42
43/*
44 * Setup CS0 (Flash).
45 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]46 write32 CS0BCR_A, CS0BCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]47
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]48 write32 CS0WCR_A, CS0WCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]49
50/*
51 * Setup CS3 (SDRAM).
52 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]53 write32 CS3BCR_A, CS3BCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]54
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]55 write32 CS3WCR_A, CS3WCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]56
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]57 write32 SDCR_A, SDCR_D1
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]58
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]59 write32 RTCSR_A, RTCSR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]60
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]61 write32 RTCNT_A, RTCNT_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]62
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]63 write32 RTCOR_A, RTCOR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]64
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]65 write32 SDCR_A, SDCR_D2
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]66
67 mov.l SDMR3_A, r1
68 mov.l SDMR3_D, r0
69 add r0, r1
70 mov #0, r0
71 mov.w r0, @r1
72
73 rts
74 nop
75
76 .align 4
77
78/*
79 * Configuration for MPR2 A.3 through A.7
80 */
81
82/*
83 * PLL Settings
84 */
85FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */
86WTCNT_D: .long 0x5A00 /* start counting at zero */
87WTCSR_D: .long 0xA507 /* divide by 4096 */
88
89/*
90 * Spansion S29GL256N11 @ 48 MHz
91 */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]92/* 1 idle cycle inserted, normal space, 16 bit */
93CS0BCR_D: .long 0x12490400
94/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
95CS0WCR_D: .long 0x00000340
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]96
97/*
98 * Samsung K4S511632B-UL75 @ 48 MHz
99 * Micron MT48LC32M16A2-75 @ 48 MHz
100 */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]101/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
102CS3BCR_D: .long 0x10004400
103/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
104CS3WCR_D: .long 0x00000091
105/* no refresh, 13 rows, 10 cols, NO bank active mode */
106SDCR_D1: .long 0x00000012
107SDCR_D2: .long 0x00000812 /* refresh */
108RTCSR_D: .long 0xA55A0008 /* 1/4, once */
109RTCNT_D: .long 0xA55A005D /* count 93 */
110RTCOR_D: .long 0xa55a005d /* count 93 */
111/* mode register CL2, burst read and SINGLE WRITE */
112SDMR3_D: .long 0x440
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]113
114/*
115 * Registers
116 */
117
118FRQCR_A: .long 0xA415FF80
119WTCNT_A: .long 0xA415FF84
120WTCSR_A: .long 0xA415FF86
121
122#define BSC_BASE 0xA4FD0000
123CS0BCR_A: .long BSC_BASE + 0x04
124CS3BCR_A: .long BSC_BASE + 0x0C
125CS0WCR_A: .long BSC_BASE + 0x24
126CS3WCR_A: .long BSC_BASE + 0x2C
127SDCR_A: .long BSC_BASE + 0x44
128RTCSR_A: .long BSC_BASE + 0x48
129RTCNT_A: .long BSC_BASE + 0x4C
130RTCOR_A: .long BSC_BASE + 0x50
131SDMR3_A: .long BSC_BASE + 0x5000