Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013 Xilinx Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #ifndef _ASM_ARCH_HARDWARE_H |
| 24 | #define _ASM_ARCH_HARDWARE_H |
| 25 | |
Michal Simek | b0bf955 | 2013-04-23 11:35:18 +0200 | [diff] [blame] | 26 | #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 |
| 27 | #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 |
| 28 | #define ZYNQ_SCU_BASEADDR 0xF8F00000 |
Michal Simek | ad2e2b7 | 2013-04-12 16:21:26 +0200 | [diff] [blame] | 29 | #define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 |
Michal Simek | 242192b | 2013-04-12 16:33:08 +0200 | [diff] [blame] | 30 | #define ZYNQ_GEM_BASEADDR0 0xE000B000 |
| 31 | #define ZYNQ_GEM_BASEADDR1 0xE000C000 |
Michal Simek | 0dd222b | 2013-04-22 14:56:49 +0200 | [diff] [blame^] | 32 | #define ZYNQ_SDHCI_BASEADDR0 0xE0100000 |
| 33 | #define ZYNQ_SDHCI_BASEADDR1 0xE0101000 |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 34 | |
| 35 | /* Reflect slcr offsets */ |
| 36 | struct slcr_regs { |
| 37 | u32 scl; /* 0x0 */ |
| 38 | u32 slcr_lock; /* 0x4 */ |
| 39 | u32 slcr_unlock; /* 0x8 */ |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 40 | u32 reserved0[75]; |
| 41 | u32 gem0_rclk_ctrl; /* 0x138 */ |
| 42 | u32 gem1_rclk_ctrl; /* 0x13c */ |
| 43 | u32 gem0_clk_ctrl; /* 0x140 */ |
| 44 | u32 gem1_clk_ctrl; /* 0x144 */ |
| 45 | u32 reserved1[46]; |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 46 | u32 pss_rst_ctrl; /* 0x200 */ |
Michal Simek | 6d46480 | 2013-02-04 12:42:25 +0100 | [diff] [blame] | 47 | u32 reserved2[15]; |
| 48 | u32 fpga_rst_ctrl; /* 0x240 */ |
| 49 | u32 reserved3[5]; |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 50 | u32 reboot_status; /* 0x258 */ |
Michal Simek | 6d46480 | 2013-02-04 12:42:25 +0100 | [diff] [blame] | 51 | u32 boot_mode; /* 0x25c */ |
| 52 | u32 reserved4[116]; |
| 53 | u32 trust_zone; /* 0x430 */ /* FIXME */ |
| 54 | u32 reserved5[115]; |
| 55 | u32 ddr_urgent; /* 0x600 */ |
| 56 | u32 reserved6[6]; |
| 57 | u32 ddr_urgent_sel; /* 0x61c */ |
| 58 | u32 reserved7[188]; |
| 59 | u32 ocm_cfg; /* 0x910 */ |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 60 | }; |
| 61 | |
Michal Simek | b0bf955 | 2013-04-23 11:35:18 +0200 | [diff] [blame] | 62 | #define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR) |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 63 | |
Michal Simek | 6d46480 | 2013-02-04 12:42:25 +0100 | [diff] [blame] | 64 | struct devcfg_regs { |
| 65 | u32 ctrl; /* 0x0 */ |
| 66 | u32 lock; /* 0x4 */ |
| 67 | u32 cfg; /* 0x8 */ |
| 68 | u32 int_sts; /* 0xc */ |
| 69 | u32 int_mask; /* 0x10 */ |
| 70 | u32 status; /* 0x14 */ |
| 71 | u32 dma_src_addr; /* 0x18 */ |
| 72 | u32 dma_dst_addr; /* 0x1c */ |
| 73 | u32 dma_src_len; /* 0x20 */ |
| 74 | u32 dma_dst_len; /* 0x24 */ |
| 75 | u32 rom_shadow; /* 0x28 */ |
| 76 | u32 reserved1[2]; |
| 77 | u32 unlock; /* 0x34 */ |
| 78 | u32 reserved2[18]; |
| 79 | u32 mctrl; /* 0x80 */ |
| 80 | u32 reserved3; |
| 81 | u32 write_count; /* 0x88 */ |
| 82 | u32 read_count; /* 0x8c */ |
| 83 | }; |
| 84 | |
Michal Simek | b0bf955 | 2013-04-23 11:35:18 +0200 | [diff] [blame] | 85 | #define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR) |
Michal Simek | 6d46480 | 2013-02-04 12:42:25 +0100 | [diff] [blame] | 86 | |
| 87 | struct scu_regs { |
| 88 | u32 reserved1[16]; |
| 89 | u32 filter_start; /* 0x40 */ |
| 90 | u32 filter_end; /* 0x44 */ |
| 91 | }; |
| 92 | |
Michal Simek | b0bf955 | 2013-04-23 11:35:18 +0200 | [diff] [blame] | 93 | #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR) |
Michal Simek | 6d46480 | 2013-02-04 12:42:25 +0100 | [diff] [blame] | 94 | |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 95 | #endif /* _ASM_ARCH_HARDWARE_H */ |