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git01.mediatek.com / filogic / uboot / 0dccde762dbed22708631c232f5557eef03dae1c / . / include / configs / ids8313.h
blob: c1b3b633e962bdc0649f9223b0f514947054ec32 [file] [log] [blame]
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100[diff] [blame]1/*
2 * (C) Copyright 2013
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * Based on:
6 * Copyright (c) 2011 IDS GmbH, Germany
7 * Sergej Stepanov <ste@ids.de>
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 */
18#define CONFIG_MPC831x
19#define CONFIG_MPC8313
20#define CONFIG_IDS8313
21
22#define CONFIG_FSL_ELBC
23
24#define CONFIG_MISC_INIT_R
25
26#define CONFIG_AUTOBOOT_KEYED
27#define CONFIG_AUTOBOOT_PROMPT \
28 "\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY
29#define CONFIG_AUTOBOOT_DELAY_STR "ids"
30#define CONFIG_BOOT_RETRY_TIME 900
31#define CONFIG_BOOT_RETRY_MIN 30
32#define CONFIG_BOOTDELAY 1
33#define CONFIG_RESET_TO_RETRY
34
35#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
36#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
37
38#define CONFIG_SYS_IMMR 0xF0000000
39
40#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
41#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
42
43/*
44 * Hardware Reset Configuration Word
45 * if CLKIN is 66.000MHz, then
46 * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
47 */
48#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
49 HRCWL_DDR_TO_SCB_CLK_2X1 |\
50 HRCWL_CSB_TO_CLKIN_2X1 |\
51 HRCWL_CORE_TO_CSB_2X1)
52
53#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
54 HRCWH_CORE_ENABLE |\
55 HRCWH_FROM_0XFFF00100 |\
56 HRCWH_BOOTSEQ_DISABLE |\
57 HRCWH_SW_WATCHDOG_DISABLE |\
58 HRCWH_ROM_LOC_LOCAL_8BIT |\
59 HRCWH_RL_EXT_LEGACY |\
60 HRCWH_TSEC1M_IN_MII |\
61 HRCWH_TSEC2M_IN_MII |\
62 HRCWH_BIG_ENDIAN)
63
64#define CONFIG_SYS_SICRH 0x00000000
65#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
66
67#define CONFIG_HWCONFIG
68
69#define CONFIG_SYS_HID0_INIT 0x000000000
70#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
71 HID0_ENABLE_INSTRUCTION_CACHE |\
72 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
73
74#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
75
76/*
77 * Definitions for initial stack pointer and data area (in DCACHE )
78 */
79#define CONFIG_SYS_INIT_RAM_LOCK
80#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
81#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
82#define CONFIG_SYS_GBL_DATA_SIZE 0x100
83#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
84 - CONFIG_SYS_GBL_DATA_SIZE)
85#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
86
87/*
88 * Local Bus LCRR and LBCR regs
89 */
90#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
91#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
92#define CONFIG_SYS_LBC_LBCR (0x00040000 |\
93 (0xFF << LBCR_BMT_SHIFT) |\
94 0xF)
95
96#define CONFIG_SYS_LBC_MRTPR 0x20000000
97
98/*
99 * Internal Definitions
100 */
101/*
102 * DDR Setup
103 */
104#define CONFIG_SYS_DDR_BASE 0x00000000
105#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
106#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
107
108/*
109 * Manually set up DDR parameters,
110 * as this board has not the SPD connected to I2C.
111 */
112#define CONFIG_SYS_DDR_SIZE 256 /* MB */
113#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
114 0x00010000 |\
115 CSCONFIG_ROW_BIT_13 |\
116 CSCONFIG_COL_BIT_10)
117
118#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
119 CSCONFIG_BANK_BIT_3)
120
121#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
122#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
123 (3 << TIMING_CFG0_WRT_SHIFT) |\
124 (3 << TIMING_CFG0_RRT_SHIFT) |\
125 (3 << TIMING_CFG0_WWT_SHIFT) |\
126 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
127 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
128 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
129 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
130#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
131 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
132 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
133 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
134 (4 << TIMING_CFG1_REFREC_SHIFT) |\
135 (4 << TIMING_CFG1_WRREC_SHIFT) |\
136 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
137 (2 << TIMING_CFG1_WRTORD_SHIFT))
138#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
139 (5 << TIMING_CFG2_CPO_SHIFT) |\
140 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
141 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
142 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
143 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
144 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
145
146#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
147 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
148
149#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
150 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
151 SDRAM_CFG_DBW_32 |\
152 SDRAM_CFG_SDRAM_TYPE_DDR2)
153
154#define CONFIG_SYS_SDRAM_CFG2 0x00401000
155#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
156 (0x0242 << SDRAM_MODE_SD_SHIFT))
157#define CONFIG_SYS_DDR_MODE_2 0x00000000
158#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
159#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
160 DDRCDR_PZ_NOMZ |\
161 DDRCDR_NZ_NOMZ |\
162 DDRCDR_ODT |\
163 DDRCDR_M_ODR |\
164 DDRCDR_Q_DRN)
165
166/*
167 * on-board devices
168 */
169#define CONFIG_TSEC1
170#define CONFIG_TSEC2
171#define CONFIG_TSEC_ENET
172#define CONFIG_NET_MULTI
173#define CONFIG_HARD_SPI
174#define CONFIG_HARD_I2C
175
176/*
177 * NOR FLASH setup
178 */
179#define CONFIG_SYS_FLASH_CFI
180#define CONFIG_FLASH_CFI_DRIVER
181#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
182#define CONFIG_FLASH_SHOW_PROGRESS 50
183#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
184
185#define CONFIG_SYS_FLASH_BASE 0xFF800000
186#define CONFIG_SYS_FLASH_SIZE 8
187#define CONFIG_SYS_FLASH_PROTECTION
188
189#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
190#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
191
192#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
193 BR_PS_8 |\
194 BR_MS_GPCM |\
195 BR_V)
196
197#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
198 OR_GPCM_SCY_10 |\
199 OR_GPCM_EHTR |\
200 OR_GPCM_TRLX |\
201 OR_GPCM_CSNT |\
202 OR_GPCM_EAD)
203#define CONFIG_SYS_MAX_FLASH_BANKS 1
204#define CONFIG_SYS_MAX_FLASH_SECT 128
205
206#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
207#define CONFIG_SYS_FLASH_WRITE_TOUT 500
208
209/*
210 * NAND FLASH setup
211 */
212#define CONFIG_SYS_NAND_BASE 0xE1000000
213#define CONFIG_SYS_MAX_NAND_DEVICE 1
214#define CONFIG_SYS_NAND_MAX_CHIPS 1
215#define CONFIG_MTD_NAND_VERIFY_WRITE
216#define CONFIG_NAND_FSL_ELBC
217#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
218#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
219#define NAND_CACHE_PAGES 64
220
221#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
222#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
223#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
224#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
225
226#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
227 (2<<BR_DECC_SHIFT) |\
228 BR_PS_8 |\
229 BR_MS_FCM |\
230 BR_V)
231
232#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
233 OR_FCM_PGS |\
234 OR_FCM_CSCT |\
235 OR_FCM_CST |\
236 OR_FCM_CHT |\
237 OR_FCM_SCY_4 |\
238 OR_FCM_TRLX |\
239 OR_FCM_EHTR |\
240 OR_FCM_RST)
241
242/*
243 * MRAM setup
244 */
245#define CONFIG_SYS_MRAM_BASE 0xE2000000
246#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
247#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
248#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
249
250#define CONFIG_SYS_OR_TIMING_MRAM
251
252#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
253 BR_PS_8 |\
254 BR_MS_GPCM |\
255 BR_V)
256
257#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
258
259/*
260 * CPLD setup
261 */
262#define CONFIG_SYS_CPLD_BASE 0xE3000000
263#define CONFIG_SYS_CPLD_SIZE 0x8000
264#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
265#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
266
267#define CONFIG_SYS_OR_TIMING_MRAM
268
269#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
270 BR_PS_8 |\
271 BR_MS_GPCM |\
272 BR_V)
273
274#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
275
276/*
277 * HW-Watchdog
278 */
279#define CONFIG_WATCHDOG 1
280#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
281
282/*
283 * I2C setup
284 */
285#define CONFIG_CMD_I2C
286#define CONFIG_SYS_I2C
287#define CONFIG_SYS_I2C_FSL
288#define CONFIG_SYS_FSL_I2C_SPEED 400000
289#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
290#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
291#define CONFIG_RTC_PCF8563
292#define CONFIG_SYS_I2C_RTC_ADDR 0x51
293
294/*
295 * SPI setup
296 */
297#ifdef CONFIG_HARD_SPI
298#define CONFIG_MPC8XXX_SPI
299#define CONFIG_CMD_SPI
300#define CONFIG_SYS_GPIO1_PRELIM
301#define CONFIG_SYS_GPIO1_DIR 0x00000001
302#define CONFIG_SYS_GPIO1_DAT 0x00000001
303#endif
304
305/*
306 * Ethernet setup
307 */
308#ifdef CONFIG_TSEC1
309#define CONFIG_HAS_ETH0
310#define CONFIG_TSEC1_NAME "TSEC0"
311#define CONFIG_SYS_TSEC1_OFFSET 0x24000
312#define TSEC1_PHY_ADDR 0x1
313#define TSEC1_FLAGS TSEC_GIGABIT
314#define TSEC1_PHYIDX 0
315#endif
316
317#ifdef CONFIG_TSEC2
318#define CONFIG_HAS_ETH1
319#define CONFIG_TSEC2_NAME "TSEC1"
320#define CONFIG_SYS_TSEC2_OFFSET 0x25000
321#define TSEC2_PHY_ADDR 0x3
322#define TSEC2_FLAGS TSEC_GIGABIT
323#define TSEC2_PHYIDX 0
324#endif
325#define CONFIG_ETHPRIME "TSEC1"
326
327/*
328 * Serial Port
329 */
330#define CONFIG_CONS_INDEX 1
331#define CONFIG_SYS_NS16550
332#define CONFIG_SYS_NS16550_SERIAL
333#define CONFIG_SYS_NS16550_REG_SIZE 1
334
335#define CONFIG_SYS_BAUDRATE_TABLE \
336 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
337#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
338#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
339#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
340
341#define CONFIG_HAS_FSL_DR_USB
342#define CONFIG_SYS_SCCR_USBDRCM 3
343
344/*
345 * BAT's
346 */
347#define CONFIG_HIGH_BATS
348
349/* DDR @ 0x00000000 */
350#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
351 BATL_PP_10)
352#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
353 BATU_BL_256M |\
354 BATU_VS |\
355 BATU_VP)
356#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
357#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
358
359/* Initial RAM @ 0xFD000000 */
360#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
361 BATL_PP_10 |\
362 BATL_GUARDEDSTORAGE)
363#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
364 BATU_BL_256K |\
365 BATU_VS |\
366 BATU_VP)
367#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
368#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
369
370/* FLASH @ 0xFF800000 */
371#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
372 BATL_PP_10 |\
373 BATL_GUARDEDSTORAGE)
374#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
375 BATU_BL_8M |\
376 BATU_VS |\
377 BATU_VP)
378#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
379 BATL_PP_10 |\
380 BATL_CACHEINHIBIT |\
381 BATL_GUARDEDSTORAGE)
382#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
383
384#define CONFIG_SYS_IBAT3L (0)
385#define CONFIG_SYS_IBAT3U (0)
386#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
387#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
388
389#define CONFIG_SYS_IBAT4L (0)
390#define CONFIG_SYS_IBAT4U (0)
391#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
392#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
393
394/* IMMRBAR @ 0xF0000000 */
395#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
396 BATL_PP_10 |\
397 BATL_CACHEINHIBIT |\
398 BATL_GUARDEDSTORAGE)
399#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
400 BATU_BL_128M |\
401 BATU_VS |\
402 BATU_VP)
403#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
404#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
405
406/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
407#define CONFIG_SYS_IBAT6L (0xE0000000 |\
408 BATL_PP_10 |\
409 BATL_GUARDEDSTORAGE)
410#define CONFIG_SYS_IBAT6U (0xE0000000 |\
411 BATU_BL_256M |\
412 BATU_VS |\
413 BATU_VP)
414#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
415#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
416
417#define CONFIG_SYS_IBAT7L (0)
418#define CONFIG_SYS_IBAT7U (0)
419#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
420#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
421
422/*
423 * U-Boot environment setup
424 */
425#include <config_cmd_default.h>
426
427#define CONFIG_CMD_DHCP
428#define CONFIG_CMD_PING
429#define CONFIG_CMD_NFS
430#define CONFIG_CMD_NAND
431#define CONFIG_CMD_FLASH
432#define CONFIG_CMD_SNTP
433#define CONFIG_CMD_MII
434#define CONFIG_CMD_DATE
435#define CONFIG_CMDLINE_EDITING
436#define CONFIG_CMD_EDITENV
437#define CONFIG_CMD_JFFS2
438#define CONFIG_BOOTP_SUBNETMASK
439#define CONFIG_BOOTP_GATEWAY
440#define CONFIG_BOOTP_HOSTNAME
441#define CONFIG_BOOTP_BOOTPATH
442#define CONFIG_BOOTP_BOOTFILESIZE
443/* pass open firmware flat tree */
444#define CONFIG_OF_LIBFDT
445#define CONFIG_OF_BOARD_SETUP
446#define CONFIG_OF_STDOUT_VIA_ALIAS
447
448/*
449 * The reserved memory
450 */
451#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
452#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
453#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
454
455/*
456 * Environment Configuration
457 */
458#define CONFIG_ENV_IS_IN_FLASH
459#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
460 + CONFIG_SYS_MONITOR_LEN)
461#define CONFIG_ENV_SIZE 0x20000
462#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
463#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
464
465
466#define CONFIG_NETDEV eth1
467#define CONFIG_HOSTNAME ids8313
468#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
469#define CONFIG_BOOTFILE "ids8313/uImage"
470#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
471#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
472#define CONFIG_LOADADDR 0x400000
473#define CONFIG_CMD_ENV_FLAGS
474#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
475
476#define CONFIG_BAUDRATE 115200
Heiko Schocher3c773bb2014-01-25 07:53:48 +0100[diff] [blame]477
478/* Initial Memory map for Linux*/
479#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
480
481/*
482 * Miscellaneous configurable options
483 */
484#define CONFIG_SYS_LONGHELP
485#define CONFIG_SYS_PROMPT "=> "
486#define CONFIG_SYS_CBSIZE 1024
487#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
488 + sizeof(CONFIG_SYS_PROMPT)+16)
489#define CONFIG_SYS_MAXARGS 16
490#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
491#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
492#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
493
494#define CONFIG_SYS_MEMTEST_START 0x00001000
495#define CONFIG_SYS_MEMTEST_END 0x00C00000
496
497#define CONFIG_SYS_LOAD_ADDR 0x100000
498#define CONFIG_MII
499#define CONFIG_LOADS_ECHO
500#define CONFIG_TIMESTAMP
501#define CONFIG_PREBOOT "echo;" \
502 "echo Type \\\"run nfsboot\\\" " \
503 "to mount root filesystem over NFS;echo"
504#undef CONFIG_BOOTARGS
505#define CONFIG_BOOTCOMMAND "run boot_cramfs"
506#undef CONFIG_SYS_LOADS_BAUD_CHANGE
507
508#define CONFIG_JFFS2_NAND
509#define CONFIG_JFFS2_DEV "0"
510
511/* mtdparts command line support */
512#define CONFIG_CMD_MTDPARTS
513#define CONFIG_FLASH_CFI_MTD
514#define CONFIG_MTD_DEVICE
515#define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash"
516#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:7m(dum)," \
517 "768k(BOOT-BIN)," \
518 "128k(BOOT-ENV),128k(BOOT-REDENV);" \
519 "e1000000.flash:-(ubi)"
520
521#define CONFIG_EXTRA_ENV_SETTINGS \
522 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
523 "ethprime=TSEC1\0" \
524 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
525 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
526 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
527 " +${filesize}; " \
528 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
529 " +${filesize}; " \
530 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
531 " ${filesize}; " \
532 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
533 " +${filesize}; " \
534 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
535 " ${filesize}\0" \
536 "console=ttyS0\0" \
537 "fdtaddr=0x780000\0" \
538 "kernel_addr=ff800000\0" \
539 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
540 "setbootargs=setenv bootargs " \
541 "root=${rootdev} rw console=${console}," \
542 "${baudrate} ${othbootargs}\0" \
543 "setipargs=setenv bootargs root=${rootdev} rw " \
544 "nfsroot=${serverip}:${rootpath} " \
545 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
546 "${netmask}:${hostname}:${netdev}:off " \
547 "console=${console},${baudrate} ${othbootargs}\0" \
548 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
549 "mtdids=" MTDIDS_DEFAULT "\0" \
550 "mtdparts=" MTDPARTS_DEFAULT "\0" \
551 "\0"
552
553#define CONFIG_NFSBOOTCOMMAND \
554 "setenv rootdev /dev/nfs;" \
555 "run setipargs;run addmtd;" \
556 "tftp ${loadaddr} ${bootfile};" \
557 "tftp ${fdtaddr} ${fdtfile};" \
558 "fdt addr ${fdtaddr};" \
559 "bootm ${loadaddr} - ${fdtaddr}"
560
561/* UBI Support */
562#define CONFIG_CMD_NAND_TRIMFFS
563#define CONFIG_CMD_UBI
564#define CONFIG_CMD_UBIFS
565#define CONFIG_RBTREE
566#define CONFIG_LZO
567#define CONFIG_MTD_PARTITIONS
568
569/* bootcount support */
570#define CONFIG_BOOTCOUNT_LIMIT
571#define CONFIG_BOOTCOUNT_I2C
572#define CONFIG_BOOTCOUNT_ALEN 1
573#define CONFIG_SYS_BOOTCOUNT_ADDR 0x9
574
575#define CONFIG_VERSION_VARIABLE
576
577#define CONFIG_FIT
578#define CONFIG_FIT_SIGNATURE
579#define CONFIG_CMD_FDT
580#define CONFIG_CMD_HASH
581#define CONFIG_RSA
582#define CONFIG_SHA1
583#define CONFIG_SHA256
584#define CONFIG_OF_CONTROL
585
586#endif /* __CONFIG_H */