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Bryan Brattlofa4d5cc22024-03-12 15:20:24 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM62P5: SoC specific initialization
4 *
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <spl.h>
9#include <asm/io.h>
10#include <asm/arch/hardware.h>
Bryan Brattlofa4d5cc22024-03-12 15:20:24 -050011#include <dm.h>
12#include <dm/uclass-internal.h>
13#include <dm/pinctrl.h>
14
Andrew Davis336b0792024-05-10 15:21:24 -050015#include "../sysfw-loader.h"
16#include "../common.h"
17
Santhosh Kumar K0dc33cd2025-01-29 17:44:02 -060018#define CTRLMMR_MCU_RST_CTRL 0x04518170
19#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK 0xFFFDFFFF
20
Bryan Brattlofa4d5cc22024-03-12 15:20:24 -050021struct fwl_data cbass_main_fwls[] = {
22 { "FSS_DAT_REG3", 7, 8 },
23};
24
25/*
26 * This uninitialized global variable would normal end up in the .bss section,
27 * but the .bss is cleared between writing and reading this variable, so move
28 * it to the .data section.
29 */
30u32 bootindex __section(".data");
31static struct rom_extended_boot_data bootdata __section(".data");
32
33static void store_boot_info_from_rom(void)
34{
35 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
36 memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
37 sizeof(struct rom_extended_boot_data));
38}
39
40static void ctrl_mmr_unlock(void)
41{
42 /* Unlock all WKUP_CTRL_MMR0 module registers */
43 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
44 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
45 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
46 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
47 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
48 mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
49 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
50 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
51
52 /* Unlock all CTRL_MMR0 module registers */
53 mmr_unlock(CTRL_MMR0_BASE, 0);
54 mmr_unlock(CTRL_MMR0_BASE, 1);
55 mmr_unlock(CTRL_MMR0_BASE, 2);
56 mmr_unlock(CTRL_MMR0_BASE, 4);
57 mmr_unlock(CTRL_MMR0_BASE, 5);
58 mmr_unlock(CTRL_MMR0_BASE, 6);
59
60 /* Unlock all MCU_CTRL_MMR0 module registers */
61 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
62 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
63 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
64 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
65 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
66 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
67
68 /* Unlock PADCFG_CTRL_MMR padconf registers */
69 mmr_unlock(PADCFG_MMR0_BASE, 1);
70 mmr_unlock(PADCFG_MMR1_BASE, 1);
71}
72
Santhosh Kumar K0dc33cd2025-01-29 17:44:02 -060073static __maybe_unused void enable_mcu_esm_reset(void)
74{
75 /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */
76 u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
77
78 stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK;
79 writel(stat, CTRLMMR_MCU_RST_CTRL);
80}
81
Bryan Brattlofa4d5cc22024-03-12 15:20:24 -050082void board_init_f(ulong dummy)
83{
84 struct udevice *dev;
85 int ret;
86
87 if (IS_ENABLED(CONFIG_CPU_V7R))
88 setup_k3_mpu_regions();
89
90 /*
91 * Cannot delay this further as there is a chance that
92 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
93 */
94 store_boot_info_from_rom();
95
96 ctrl_mmr_unlock();
97
98 /* Init DM early */
99 ret = spl_early_init();
100 if (ret)
101 panic("spl_early_init() failed: %d\n", ret);
102
103 /*
104 * Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and
105 * MAIN_UART1 modules and continue regardless of the result of pinctrl.
106 * Do this without probing the device, but instead by searching the
107 * device that would request the given sequence number if probed. The
108 * UARTs will be used by the DM firmware and TIFS firmware images
109 * respectively and the firmware depend on SPL to initialize the pin
110 * settings.
111 */
112 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
113 if (!ret)
114 pinctrl_select_state(dev, "default");
115
116 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
117 if (!ret)
118 pinctrl_select_state(dev, "default");
119
120 /*
121 * Allow establishing an early console as required for example when
122 * doing a UART-based boot. Note that this console may not "survive"
123 * through a SYSFW PM-init step and will need a re-init in some way
124 * due to changing module clock frequencies.
125 */
126 if (IS_ENABLED(CONFIG_K3_EARLY_CONS)) {
127 ret = early_console_init();
128 if (ret)
129 panic("early_console_init() failed: %d\n", ret);
130 }
131
132 /*
133 * Configure and start up system controller firmware. Provide
134 * the U-Boot console init function to the SYSFW post-PM configuration
135 * callback hook, effectively switching on (or over) the console
136 * output.
137 */
138 if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
139 ret = is_rom_loaded_sysfw(&bootdata);
140 if (!ret)
141 panic("ROM has not loaded TIFS firmware\n");
142
143 k3_sysfw_loader(true, NULL, NULL);
144
145 /* Disable ROM configured firewalls */
146 remove_fwl_configs(cbass_main_fwls,
147 ARRAY_SIZE(cbass_main_fwls));
148 }
149
150 /*
151 * Force probe of clk_k3 driver here to ensure basic default clock
152 * configuration is always done.
153 */
154 if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
155 ret = uclass_get_device_by_driver(UCLASS_CLK,
156 DM_DRIVER_GET(ti_clk),
157 &dev);
158 if (ret)
159 printf("Failed to initialize clk-k3!\n");
160 }
161
162 preloader_console_init();
163
164 /* Output System Firmware version info */
165 k3_sysfw_print_ver();
166
167 if (IS_ENABLED(CONFIG_K3_AM62A_DDRSS)) {
168 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
169 if (ret)
170 panic("DRAM init failed: %d\n", ret);
171 }
172
Santhosh Kumar K0dc33cd2025-01-29 17:44:02 -0600173 if (IS_ENABLED(CONFIG_ESM_K3)) {
174 /* Probe/configure ESM0 */
175 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
176 if (ret)
177 printf("esm main init failed: %d\n", ret);
178
179 /* Probe/configure MCUESM */
180 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
181 if (ret)
182 printf("esm mcu init failed: %d\n", ret);
183
184 enable_mcu_esm_reset();
185 }
186
Bryan Brattlofa4d5cc22024-03-12 15:20:24 -0500187 spl_enable_cache();
Jayesh Choudharye0535272024-11-26 12:36:12 +0530188
189 setup_qos();
Bryan Brattlofa4d5cc22024-03-12 15:20:24 -0500190 debug("am62px_init: %s done\n", __func__);
191}
192
193u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
194{
195 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
196 u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
197 MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
198 u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
199 MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
200
201 switch (bootmode) {
202 case BOOT_DEVICE_EMMC:
203 return MMCSD_MODE_EMMCBOOT;
204 case BOOT_DEVICE_MMC:
205 if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)
206 return MMCSD_MODE_RAW;
207 default:
208 return MMCSD_MODE_FS;
209 }
210}
211
212static u32 __get_backup_bootmedia(u32 devstat)
213{
214 u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
215 MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
216 u32 bkup_bootmode_cfg =
217 (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
218 MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
219
220 switch (bkup_bootmode) {
221 case BACKUP_BOOT_DEVICE_UART:
222 return BOOT_DEVICE_UART;
223
224 case BACKUP_BOOT_DEVICE_USB:
225 return BOOT_DEVICE_USB;
226
227 case BACKUP_BOOT_DEVICE_ETHERNET:
228 return BOOT_DEVICE_ETHERNET;
229
230 case BACKUP_BOOT_DEVICE_MMC:
231 if (bkup_bootmode_cfg)
232 return BOOT_DEVICE_MMC2;
233 return BOOT_DEVICE_MMC1;
234
235 case BACKUP_BOOT_DEVICE_SPI:
236 return BOOT_DEVICE_SPI;
237
238 case BACKUP_BOOT_DEVICE_I2C:
239 return BOOT_DEVICE_I2C;
240
241 case BACKUP_BOOT_DEVICE_DFU:
242 if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
243 return BOOT_DEVICE_USB;
244 return BOOT_DEVICE_DFU;
245 };
246
247 return BOOT_DEVICE_RAM;
248}
249
250static u32 __get_primary_bootmedia(u32 devstat)
251{
252 u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
253 MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
254 u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
255 MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
256
257 switch (bootmode) {
258 case BOOT_DEVICE_OSPI:
259 fallthrough;
260 case BOOT_DEVICE_QSPI:
261 fallthrough;
262 case BOOT_DEVICE_XSPI:
263 fallthrough;
264 case BOOT_DEVICE_SPI:
265 return BOOT_DEVICE_SPI;
266
267 case BOOT_DEVICE_ETHERNET_RGMII:
268 fallthrough;
269 case BOOT_DEVICE_ETHERNET_RMII:
270 return BOOT_DEVICE_ETHERNET;
271
272 case BOOT_DEVICE_EMMC:
273 return BOOT_DEVICE_MMC1;
274
275 case BOOT_DEVICE_SPI_NAND:
276 return BOOT_DEVICE_SPINAND;
277
278 case BOOT_DEVICE_MMC:
279 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
280 MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
281 return BOOT_DEVICE_MMC2;
282 return BOOT_DEVICE_MMC1;
283
284 case BOOT_DEVICE_DFU:
285 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
286 MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
287 return BOOT_DEVICE_USB;
288 return BOOT_DEVICE_DFU;
289
290 case BOOT_DEVICE_NOBOOT:
291 return BOOT_DEVICE_RAM;
292 }
293
294 return bootmode;
295}
296
297u32 spl_boot_device(void)
298{
299 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
300 u32 bootmedia;
301
302 if (bootindex == K3_PRIMARY_BOOTMODE)
303 bootmedia = __get_primary_bootmedia(devstat);
304 else
305 bootmedia = __get_backup_bootmedia(devstat);
306
307 debug("am62px_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
308 __func__, devstat, bootmedia, bootindex);
309 return bootmedia;
310}