Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 2 | /* |
Kumar Gala | a9db4ec | 2011-01-11 00:52:35 -0600 | [diff] [blame] | 3 | * Copyright 2004, 2011 Freescale Semiconductor. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 4 | * (C) Copyright 2002,2003 Motorola,Inc. |
| 5 | * Xianghua Xiao <X.Xiao@motorola.com> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 8 | /* |
| 9 | * mpc8560ads board configuration file |
| 10 | * |
| 11 | * Please refer to doc/README.mpc85xx for more info. |
| 12 | * |
| 13 | * Make sure you change the MAC address and other network params first, |
Joe Hershberger | 76f353e | 2015-05-04 14:55:14 -0500 | [diff] [blame] | 14 | * search for CONFIG_SERVERIP, etc. in this file. |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef __CONFIG_H |
| 18 | #define __CONFIG_H |
| 19 | |
| 20 | /* High Level Configuration Options */ |
Jon Loeliger | f5ad378 | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 21 | #define CONFIG_CPM2 1 /* has CPM2 */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 22 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 23 | /* |
| 24 | * default CCARBAR is at 0xff700000 |
| 25 | * assume U-Boot is less than 0.5MB |
| 26 | */ |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 27 | |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 28 | #define CONFIG_PCI_INDIRECT_BRIDGE |
Kumar Gala | 7738d5c | 2008-10-21 11:33:58 -0500 | [diff] [blame] | 29 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Andy Fleming | 8ed1196 | 2007-05-08 17:27:43 -0500 | [diff] [blame] | 30 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 31 | #define CONFIG_ENV_OVERWRITE |
Peter Tyser | d3d9a50 | 2009-09-16 22:03:08 -0500 | [diff] [blame] | 32 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 33 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 34 | /* |
| 35 | * sysclk for MPC85xx |
| 36 | * |
| 37 | * Two valid values are: |
| 38 | * 33000000 |
| 39 | * 66000000 |
| 40 | * |
| 41 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 42 | * is likely the desired value here, so that is now the default. |
| 43 | * The board, however, can run at 66MHz. In any event, this value |
| 44 | * must match the settings of some switches. Details can be found |
| 45 | * in the README.mpc85xxads. |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 46 | */ |
| 47 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 48 | #ifndef CONFIG_SYS_CLK_FREQ |
| 49 | #define CONFIG_SYS_CLK_FREQ 33000000 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 50 | #endif |
| 51 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 52 | /* |
| 53 | * These can be toggled for performance analysis, otherwise use default. |
| 54 | */ |
| 55 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 56 | #define CONFIG_BTB /* toggle branch predition */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 57 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 58 | #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 59 | |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 60 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
| 61 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 62 | |
Jon Loeliger | 99d5071 | 2008-03-18 11:12:44 -0500 | [diff] [blame] | 63 | /* DDR Setup */ |
Jon Loeliger | 99d5071 | 2008-03-18 11:12:44 -0500 | [diff] [blame] | 64 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 65 | #define CONFIG_DDR_SPD |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 66 | |
Jon Loeliger | 99d5071 | 2008-03-18 11:12:44 -0500 | [diff] [blame] | 67 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 68 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 69 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 70 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 71 | |
Jon Loeliger | 99d5071 | 2008-03-18 11:12:44 -0500 | [diff] [blame] | 72 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 73 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 74 | |
Jon Loeliger | 99d5071 | 2008-03-18 11:12:44 -0500 | [diff] [blame] | 75 | /* I2C addresses of SPD EEPROMs */ |
| 76 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 77 | |
Jon Loeliger | 99d5071 | 2008-03-18 11:12:44 -0500 | [diff] [blame] | 78 | /* These are used when DDR doesn't use SPD. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ |
| 80 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ |
| 81 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 |
| 82 | #define CONFIG_SYS_DDR_TIMING_1 0x37344321 |
| 83 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ |
| 84 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
| 85 | #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ |
| 86 | #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 87 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 88 | /* |
| 89 | * SDRAM on the Local Bus |
| 90 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 91 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
| 92 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 93 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 94 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
| 95 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 96 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ |
| 98 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 99 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ |
| 100 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 101 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 102 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 103 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 104 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 105 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 107 | #define CONFIG_SYS_RAMBOOT |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 108 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | #undef CONFIG_SYS_RAMBOOT |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 110 | #endif |
| 111 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 112 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 113 | |
| 114 | #undef CONFIG_CLOCKS_IN_MHZ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 115 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 116 | /* |
| 117 | * Local Bus Definitions |
| 118 | */ |
| 119 | |
| 120 | /* |
| 121 | * Base Register 2 and Option Register 2 configure SDRAM. |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 122 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 123 | * |
| 124 | * For BR2, need: |
| 125 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| 126 | * port-size = 32-bits = BR2[19:20] = 11 |
| 127 | * no parity checking = BR2[21:22] = 00 |
| 128 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 129 | * Valid = BR[31] = 1 |
| 130 | * |
| 131 | * 0 4 8 12 16 20 24 28 |
| 132 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| 133 | * |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 135 | * FIXME: the top 17 bits of BR2. |
| 136 | */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 137 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 139 | |
| 140 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 141 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 142 | * |
| 143 | * For OR2, need: |
| 144 | * 64MB mask for AM, OR2[0:7] = 1111 1100 |
| 145 | * XAM, OR2[17:18] = 11 |
| 146 | * 9 columns OR2[19-21] = 010 |
| 147 | * 13 rows OR2[23-25] = 100 |
| 148 | * EAD set for extra time OR[31] = 1 |
| 149 | * |
| 150 | * 0 4 8 12 16 20 24 28 |
| 151 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
| 152 | */ |
| 153 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 155 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 156 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
| 157 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ |
| 158 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 159 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 160 | |
Kumar Gala | 727c6a6 | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 161 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ |
| 162 | | LSDMR_RFCR5 \ |
| 163 | | LSDMR_PRETOACT3 \ |
| 164 | | LSDMR_ACTTORW3 \ |
| 165 | | LSDMR_BL8 \ |
| 166 | | LSDMR_WRC2 \ |
| 167 | | LSDMR_CL3 \ |
| 168 | | LSDMR_RFEN \ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 169 | ) |
| 170 | |
| 171 | /* |
| 172 | * SDRAM Controller configuration sequence. |
| 173 | */ |
Kumar Gala | 727c6a6 | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 174 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
| 175 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) |
| 176 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) |
| 177 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) |
| 178 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 179 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 180 | /* |
| 181 | * 32KB, 8-bit wide for ADS config reg |
| 182 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 183 | #define CONFIG_SYS_BR4_PRELIM 0xf8000801 |
| 184 | #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 |
| 185 | #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 186 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 188 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 189 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 190 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 191 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 193 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 194 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 195 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 196 | |
| 197 | /* Serial Port */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 198 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
| 199 | #undef CONFIG_CONS_NONE /* define if console on something else */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 200 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 201 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 202 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 203 | |
Jon Loeliger | 43d818f | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 204 | /* |
| 205 | * I2C |
| 206 | */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 207 | #define CONFIG_SYS_I2C |
| 208 | #define CONFIG_SYS_I2C_FSL |
| 209 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 210 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 211 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 212 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 213 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 214 | /* RapidIO MMU */ |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 215 | #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 216 | #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 217 | #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 218 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 219 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 220 | /* |
| 221 | * General PCI |
Sergei Shtylyov | 6ffad93 | 2006-12-27 22:07:15 +0300 | [diff] [blame] | 222 | * Memory space is mapped 1-1, but I/O space must start from 0. |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 223 | */ |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 224 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 225 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 226 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 227 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 228 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
Kumar Gala | 64bb6d1 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 229 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 230 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
| 231 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 232 | |
| 233 | #if defined(CONFIG_PCI) |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 234 | #undef CONFIG_EEPRO100 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 235 | #undef CONFIG_TULIP |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 236 | |
| 237 | #if !defined(CONFIG_PCI_PNP) |
| 238 | #define PCI_ENET0_IOADDR 0xe0000000 |
| 239 | #define PCI_ENET0_MEMADDR 0xe0000000 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 240 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 241 | #endif |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 242 | |
| 243 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 244 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 245 | |
| 246 | #endif /* CONFIG_PCI */ |
| 247 | |
Andy Fleming | 8ed1196 | 2007-05-08 17:27:43 -0500 | [diff] [blame] | 248 | #ifdef CONFIG_TSEC_ENET |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 249 | |
Kim Phillips | 177e58f | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 250 | #define CONFIG_TSEC1 1 |
| 251 | #define CONFIG_TSEC1_NAME "TSEC0" |
| 252 | #define CONFIG_TSEC2 1 |
| 253 | #define CONFIG_TSEC2_NAME "TSEC1" |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 254 | #define TSEC1_PHY_ADDR 0 |
| 255 | #define TSEC2_PHY_ADDR 1 |
| 256 | #define TSEC1_PHYIDX 0 |
| 257 | #define TSEC2_PHYIDX 0 |
Andy Fleming | 09b88df | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 258 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 259 | #define TSEC2_FLAGS TSEC_GIGABIT |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 260 | |
| 261 | /* Options are: TSEC[0-1] */ |
| 262 | #define CONFIG_ETHPRIME "TSEC0" |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 263 | |
Andy Fleming | 8ed1196 | 2007-05-08 17:27:43 -0500 | [diff] [blame] | 264 | #endif /* CONFIG_TSEC_ENET */ |
| 265 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 266 | #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 267 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 268 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 269 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
| 270 | |
| 271 | #if (CONFIG_ETHER_INDEX == 2) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 272 | /* |
| 273 | * - Rx-CLK is CLK13 |
| 274 | * - Tx-CLK is CLK14 |
| 275 | * - Select bus for bd/buffers |
| 276 | * - Full duplex |
| 277 | */ |
Mike Frysinger | 109de97 | 2011-10-17 05:38:58 +0000 | [diff] [blame] | 278 | #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
| 279 | #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 280 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
| 281 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 282 | #define FETH2_RST 0x01 |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 283 | #elif (CONFIG_ETHER_INDEX == 3) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 284 | /* need more definitions here for FE3 */ |
| 285 | #define FETH3_RST 0x80 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 286 | #endif /* CONFIG_ETHER_INDEX */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 287 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 288 | /* |
| 289 | * GPIO pins used for bit-banged MII communications |
| 290 | */ |
| 291 | #define MDIO_PORT 2 /* Port C */ |
Luigi 'Comio' Mantellini | 25e3072 | 2009-10-10 12:42:22 +0200 | [diff] [blame] | 292 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
| 293 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) |
| 294 | #define MDC_DECLARE MDIO_DECLARE |
| 295 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 296 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
| 297 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) |
| 298 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) |
| 299 | |
| 300 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ |
| 301 | else iop->pdat &= ~0x00400000 |
| 302 | |
| 303 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ |
| 304 | else iop->pdat &= ~0x00200000 |
| 305 | |
| 306 | #define MIIDELAY udelay(1) |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 307 | |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 308 | #endif |
| 309 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 310 | /* |
| 311 | * Environment |
| 312 | */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 313 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 314 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 315 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 316 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 317 | /* |
Jon Loeliger | ed26c74 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 318 | * BOOTP options |
| 319 | */ |
| 320 | #define CONFIG_BOOTP_BOOTFILESIZE |
Jon Loeliger | ed26c74 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 321 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 322 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 323 | |
| 324 | /* |
| 325 | * Miscellaneous configurable options |
| 326 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 327 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 328 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 329 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 330 | |
| 331 | /* |
| 332 | * For booting Linux, the board info and command line data |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 333 | * have to be in the first 64 MB of memory, since this is |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 334 | * the maximum mapped by the Linux kernel during initialization. |
| 335 | */ |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 336 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 337 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 338 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 339 | #if defined(CONFIG_CMD_KGDB) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 340 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 341 | #endif |
| 342 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 343 | /* |
| 344 | * Environment Configuration |
| 345 | */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 346 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
Andy Fleming | 458c389 | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 347 | #define CONFIG_HAS_ETH0 |
wdenk | 54070ab | 2004-12-31 09:32:47 +0000 | [diff] [blame] | 348 | #define CONFIG_HAS_ETH1 |
wdenk | 54070ab | 2004-12-31 09:32:47 +0000 | [diff] [blame] | 349 | #define CONFIG_HAS_ETH2 |
Kumar Gala | f2982fa | 2007-11-28 22:40:31 -0600 | [diff] [blame] | 350 | #define CONFIG_HAS_ETH3 |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 351 | #endif |
| 352 | |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 353 | #define CONFIG_IPADDR 192.168.1.253 |
| 354 | |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 355 | #define CONFIG_HOSTNAME "unknown" |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 356 | #define CONFIG_ROOTPATH "/nfsroot" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 357 | #define CONFIG_BOOTFILE "your.uImage" |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 358 | |
| 359 | #define CONFIG_SERVERIP 192.168.1.1 |
| 360 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 361 | #define CONFIG_NETMASK 255.255.255.0 |
| 362 | |
| 363 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
| 364 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 365 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Andy Fleming | 29e484e | 2008-07-14 20:04:40 -0500 | [diff] [blame] | 366 | "netdev=eth0\0" \ |
| 367 | "consoledev=ttyCPM\0" \ |
| 368 | "ramdiskaddr=1000000\0" \ |
| 369 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
| 370 | "fdtaddr=400000\0" \ |
| 371 | "fdtfile=mpc8560ads.dtb\0" |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 372 | |
wdenk | 492b9e7 | 2004-08-01 23:02:45 +0000 | [diff] [blame] | 373 | #define CONFIG_NFSBOOTCOMMAND \ |
Andy Fleming | 29e484e | 2008-07-14 20:04:40 -0500 | [diff] [blame] | 374 | "setenv bootargs root=/dev/nfs rw " \ |
| 375 | "nfsroot=$serverip:$rootpath " \ |
| 376 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 377 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 378 | "tftp $loadaddr $bootfile;" \ |
| 379 | "tftp $fdtaddr $fdtfile;" \ |
| 380 | "bootm $loadaddr - $fdtaddr" |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 381 | |
| 382 | #define CONFIG_RAMBOOTCOMMAND \ |
Andy Fleming | 29e484e | 2008-07-14 20:04:40 -0500 | [diff] [blame] | 383 | "setenv bootargs root=/dev/ram rw " \ |
| 384 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 385 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 386 | "tftp $loadaddr $bootfile;" \ |
| 387 | "tftp $fdtaddr $fdtfile;" \ |
| 388 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
wdenk | 13eb221 | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 389 | |
| 390 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 391 | |
| 392 | #endif /* __CONFIG_H */ |