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git01.mediatek.com / filogic / uboot / 0d63f7cef9ec554f6ba40ea134ac3e3b05aa06a3 / . / post / lib_powerpc / threei.c
blob: f6d90525325ec3f5f6a3cf10f9ac3a2511a415ad [file] [log] [blame]
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]6 */
7
8#include <common.h>
9
10/*
11 * CPU test
12 * Ternary instructions instr rA,rS,UIMM
13 *
14 * Logic instructions: ori, oris, xori, xoris
15 *
16 * The test contains a pre-built table of instructions, operands and
17 * expected results. For each table entry, the test will cyclically use
18 * different sets of operand registers and result registers.
19 */
20
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]21#include <post.h>
22#include "cpu_asm.h"
23
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]24#if CONFIG_POST & CONFIG_SYS_POST_CPU
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]25
26extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
27extern ulong cpu_post_makecr (long v);
28
29static struct cpu_post_threei_s
30{
31 ulong cmd;
32 ulong op1;
33 ushort op2;
34 ulong res;
35} cpu_post_threei_table[] =
36{
37 {
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]38 OP_ORI,
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]39 0x80000000,
40 0xffff,
41 0x8000ffff
42 },
43 {
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]44 OP_ORIS,
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]45 0x00008000,
46 0xffff,
47 0xffff8000
48 },
49 {
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]50 OP_XORI,
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]51 0x8000ffff,
52 0xffff,
53 0x80000000
54 },
55 {
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]56 OP_XORIS,
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]57 0x00008000,
58 0xffff,
59 0xffff8000
60 },
61};
Mike Frysinger83a687b2011-05-10 07:28:35 +0000[diff] [blame]62static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]63
64int cpu_post_test_threei (void)
65{
66 int ret = 0;
67 unsigned int i, reg;
68 int flag = disable_interrupts();
69
70 for (i = 0; i < cpu_post_threei_size && ret == 0; i++)
71 {
72 struct cpu_post_threei_s *test = cpu_post_threei_table + i;
73
74 for (reg = 0; reg < 32 && ret == 0; reg++)
75 {
76 unsigned int reg0 = (reg + 0) % 32;
77 unsigned int reg1 = (reg + 1) % 32;
78 unsigned int stk = reg < 16 ? 31 : 15;
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]79 unsigned long code[] =
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]80 {
81 ASM_STW(stk, 1, -4),
82 ASM_ADDI(stk, 1, -16),
83 ASM_STW(3, stk, 8),
84 ASM_STW(reg0, stk, 4),
85 ASM_STW(reg1, stk, 0),
86 ASM_LWZ(reg0, stk, 8),
87 ASM_11IX(test->cmd, reg1, reg0, test->op2),
88 ASM_STW(reg1, stk, 8),
89 ASM_LWZ(reg1, stk, 0),
90 ASM_LWZ(reg0, stk, 4),
91 ASM_LWZ(3, stk, 8),
92 ASM_ADDI(1, stk, 16),
93 ASM_LWZ(stk, 1, -4),
94 ASM_BLR,
95 };
96 ulong res;
97 ulong cr;
98
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]99 cr = 0;
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]100 cpu_post_exec_21 (code, & cr, & res, test->op1);
101
102 ret = res == test->res && cr == 0 ? 0 : -1;
103
104 if (ret != 0)
105 {
106 post_log ("Error at threei test %d !\n", i);
107 }
108 }
109 }
110
111 if (flag)
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]112 enable_interrupts();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]113
114 return ret;
115}
116
117#endif