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git01.mediatek.com / filogic / uboot / 0d5bd0762ed6a6fd4960713ac026ad937ba049db / . / include / configs / mx6sabreauto.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Fabio Estevamafe20bf2012-09-24 08:09:33 +0000[diff] [blame]2/*
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 *
Otavio Salvadorc0bfaab2012-10-02 09:22:10 +0000[diff] [blame]5 * Configuration settings for the Freescale i.MX6Q SabreAuto board.
Fabio Estevamafe20bf2012-09-24 08:09:33 +0000[diff] [blame]6 */
7
Vanessa Maegimad6362d92017-06-29 09:33:46 -0300[diff] [blame]8#ifndef __MX6SABREAUTO_CONFIG_H
9#define __MX6SABREAUTO_CONFIG_H
Fabio Estevamafe20bf2012-09-24 08:09:33 +0000[diff] [blame]10
Vanessa Maegima65779d32017-06-29 09:33:45 -0300[diff] [blame]11#ifdef CONFIG_SPL
12#include "imx6_spl.h"
13#endif
14
Fabio Estevamafe20bf2012-09-24 08:09:33 +0000[diff] [blame]15#define CONFIG_MACH_TYPE 3529
16#define CONFIG_MXC_UART_BASE UART4_BASE
Simon Glass4694a742016-10-17 20:12:39 -0600[diff] [blame]17#define CONSOLE_DEV "ttymxc3"
Fabio Estevamafe20bf2012-09-24 08:09:33 +0000[diff] [blame]18
Knut Wohlrab54dbf152013-01-21 23:11:21 +0000[diff] [blame]19/* USB Configs */
Troy Kiskyed72a9e2013-10-10 15:27:59 -0700[diff] [blame]20#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
21#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
Knut Wohlrab54dbf152013-01-21 23:11:21 +0000[diff] [blame]22#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
23#define CONFIG_MXC_USB_FLAGS 0
24
Ye.Li700020e2014-10-30 18:53:49 +0800[diff] [blame]25#define CONFIG_PCA953X
26#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
27
Pierre Aubertec10aed2013-06-04 09:00:15 +0200[diff] [blame]28#include "mx6sabre_common.h"
Otavio Salvador1c0b9be2012-09-26 11:37:01 +0000[diff] [blame]29
Diego Dorta614c2832017-07-07 15:38:34 -0300[diff] [blame]30/* Falcon Mode */
31#ifdef CONFIG_SPL_OS_BOOT
32#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
33#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
Diego Dorta614c2832017-07-07 15:38:34 -0300[diff] [blame]34#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
Diego Dorta614c2832017-07-07 15:38:34 -0300[diff] [blame]35
36/* Falcon Mode - MMC support: args@1MB kernel@2MB */
37#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
38#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
39#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
40#endif
41
Fabio Estevama03035f2017-07-10 15:59:11 -0300[diff] [blame]42#ifdef CONFIG_MTD_NOR_FLASH
Fabio Estevam2623cb12014-11-14 11:27:23 -0200[diff] [blame]43#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
44#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
45#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
46#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Fabio Estevam2623cb12014-11-14 11:27:23 -0200[diff] [blame]47#define CONFIG_SYS_FLASH_EMPTY_INFO
Fabio Estevam15d61f12016-12-15 16:00:11 -0200[diff] [blame]48#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Fabio Estevama03035f2017-07-10 15:59:11 -0300[diff] [blame]49#endif
Fabio Estevam2623cb12014-11-14 11:27:23 -0200[diff] [blame]50
Shawn Guo7e5e8332012-12-30 14:14:59 +0000[diff] [blame]51#define CONFIG_SYS_FSL_USDHC_NUM 2
52#if defined(CONFIG_ENV_IS_IN_MMC)
53#define CONFIG_SYS_MMC_ENV_DEV 0
54#endif
55
Renato Friasbf084322013-05-13 18:01:12 +0000[diff] [blame]56/* I2C Configs */
trem03997412013-09-21 18:13:36 +0200[diff] [blame]57#define CONFIG_SYS_I2C
58#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200[diff] [blame]59#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
60#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf1a52162015-03-20 10:20:40 -0700[diff] [blame]61#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Renato Friasbf084322013-05-13 18:01:12 +0000[diff] [blame]62#define CONFIG_SYS_I2C_SPEED 100000
63
Ye.Li4a1f9222014-11-12 14:02:05 +0800[diff] [blame]64/* NAND stuff */
Ye.Li4a1f9222014-11-12 14:02:05 +0800[diff] [blame]65#define CONFIG_SYS_MAX_NAND_DEVICE 1
66#define CONFIG_SYS_NAND_BASE 0x40000000
67#define CONFIG_SYS_NAND_5_ADDR_CYCLE
68#define CONFIG_SYS_NAND_ONFI_DETECTION
69
70/* DMA stuff, needed for GPMI/MXS NAND support */
Ye.Li4a1f9222014-11-12 14:02:05 +0800[diff] [blame]71
Ye.Licfaa23b2014-11-06 16:29:02 +0800[diff] [blame]72/* PMIC */
73#define CONFIG_POWER
74#define CONFIG_POWER_I2C
75#define CONFIG_POWER_PFUZE100
76#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
77
Vanessa Maegimad6362d92017-06-29 09:33:46 -0300[diff] [blame]78#endif /* __MX6SABREAUTO_CONFIG_H */