arch/arm/dts/uniphier-pro5.dtsi

/*
 * Device Tree Source for UniPhier Pro5 SoC
 *
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

/ {
	compatible = "socionext,uniphier-pro5";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};
	};

	cpu_opp: opp_table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			clock-latency-ns = <300>;
		};
		opp-116667000 {
			opp-hz = /bits/ 64 <116667000>;
			clock-latency-ns = <300>;
		};
		opp-150000000 {
			opp-hz = /bits/ 64 <150000000>;
			clock-latency-ns = <300>;
		};
		opp-175000000 {
			opp-hz = /bits/ 64 <175000000>;
			clock-latency-ns = <300>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			clock-latency-ns = <300>;
		};
		opp-233334000 {
			opp-hz = /bits/ 64 <233334000>;
			clock-latency-ns = <300>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			clock-latency-ns = <300>;
		};
		opp-350000000 {
			opp-hz = /bits/ 64 <350000000>;
			clock-latency-ns = <300>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			clock-latency-ns = <300>;
		};
		opp-466667000 {
			opp-hz = /bits/ 64 <466667000>;
			clock-latency-ns = <300>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			clock-latency-ns = <300>;
		};
		opp-700000000 {
			opp-hz = /bits/ 64 <700000000>;
			clock-latency-ns = <300>;
		};
		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			clock-latency-ns = <300>;
		};
		opp-933334000 {
			opp-hz = /bits/ 64 <933334000>;
			clock-latency-ns = <300>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <300>;
		};
		opp-1400000000 {
			opp-hz = /bits/ 64 <1400000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <20000000>;
		};

		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;
		u-boot,dm-pre-reloc;

		l2: l2-cache@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
			      <0x506c0000 0x400>;
			interrupts = <0 190 4>, <0 191 4>;
			cache-unified;
			cache-size = <(2 * 1024 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <128>;
			cache-level = <2>;
			next-level-cache = <&l3>;
		};

		l3: l3-cache@500c8000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
			      <0x506c8000 0x400>;
			interrupts = <0 174 4>, <0 175 4>;
			cache-unified;
			cache-size = <(2 * 1024 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <256>;
			cache-level = <3>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			clock-frequency = <73728000>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			clock-frequency = <73728000>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			clock-frequency = <73728000>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			clock-frequency = <73728000>;
		};

		port0x: gpio@55000008 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000008 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port1x: gpio@55000010 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000010 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port2x: gpio@55000018 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000018 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port3x: gpio@55000020 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000020 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port4: gpio@55000028 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000028 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port5x: gpio@55000030 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000030 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port6x: gpio@55000038 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000038 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port7x: gpio@55000040 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000040 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port8x: gpio@55000048 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000048 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port9x: gpio@55000050 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000050 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port10x: gpio@55000058 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000058 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port11x: gpio@55000060 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000060 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port12x: gpio@55000068 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000068 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port13x: gpio@55000070 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000070 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port14x: gpio@55000078 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000078 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port17x: gpio@550000a0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000a0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port18x: gpio@550000a8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000a8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port19x: gpio@550000b0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000b0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port20x: gpio@550000b8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000b8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port21x: gpio@550000c0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000c0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port22x: gpio@550000c8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000c8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port23x: gpio@550000d0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000d0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port24x: gpio@550000d8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000d8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port25x: gpio@550000e0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000e0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port26x: gpio@550000e8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000e8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port27x: gpio@550000f0 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000f0 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port28x: gpio@550000f8 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x550000f8 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port29x: gpio@55000100 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000100 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		port30x: gpio@55000108 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000108 0x8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			clock-frequency = <100000>;
		};

		/* i2c4 does not exist */

		/* chip-internal connection for DMD */
		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&peri_clk 9>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 26 4>;
			clocks = <&peri_clk 10>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-pro5-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x800>;
			u-boot,dm-pre-reloc;

			sd_clk: clock {
				compatible = "socionext,uniphier-pro5-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-pro5-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-pro5-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-pro5-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-pro5-peri-reset";
				#reset-cells = <1>;
			};
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-pro5-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;
			u-boot,dm-pre-reloc;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-pro5-pinctrl";
				u-boot,dm-pre-reloc;
			};
		};

		aidet@5fc20000 {
			compatible = "simple-mfd", "syscon";
			reg = <0x5fc20000 0x200>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <1 11 0x304>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <1 13 0x304>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-pro5-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-pro5-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-pro5-reset";
				#reset-cells = <1>;
			};
		};

		usb0: usb@65b00000 {
			compatible = "socionext,uniphier-pro5-dwc3";
			status = "disabled";
			reg = <0x65b00000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			dwc3@65a00000 {
				compatible = "snps,dwc3";
				reg = <0x65a00000 0x10000>;
				interrupts = <0 134 4>;
				tx-fifo-resize;
			};
		};

		usb1: usb@65d00000 {
			compatible = "socionext,uniphier-pro5-dwc3";
			status = "disabled";
			reg = <0x65d00000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
			dwc3@65c00000 {
				compatible = "snps,dwc3";
				reg = <0x65c00000 0x10000>;
				interrupts = <0 137 4>;
				tx-fifo-resize;
			};
		};

		nand: nand@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5b";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			clocks = <&sys_clk 2>;
			nand-ecc-strength = <8>;
		};

		emmc: sdhc@68400000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x68400000 0x800>;
			interrupts = <0 78 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&sd_clk 1>;
			reset-names = "host";
			resets = <&sd_rst 1>;
			bus-width = <8>;
			non-removable;
			cap-mmc-highspeed;
			cap-mmc-hw-reset;
			no-3-3-v;
		};

		sd: sdhc@68800000 {
			compatible = "socionext,uniphier-sdhc";
			status = "disabled";
			reg = <0x68800000 0x800>;
			interrupts = <0 76 4>;
			pinctrl-names = "default", "1.8v";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_1v8>;
			clocks = <&sd_clk 0>;
			reset-names = "host";
			resets = <&sd_rst 0>;
			bus-width = <4>;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
		};
	};
};

/include/ "uniphier-pinctrl.dtsi"