Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Graeme Russ, graeme.russ@gmail.com. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <asm/io.h> |
| 26 | #include <asm/ic/sc520.h> |
Graeme Russ | a1eeccf | 2010-04-24 00:05:55 +1000 | [diff] [blame] | 27 | #include <net.h> |
| 28 | #include <netdev.h> |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 29 | |
| 30 | #ifdef CONFIG_HW_WATCHDOG |
| 31 | #include <watchdog.h> |
| 32 | #endif |
| 33 | |
| 34 | #include "hardware.h" |
| 35 | |
| 36 | DECLARE_GLOBAL_DATA_PTR; |
| 37 | |
| 38 | #undef SC520_CDP_DEBUG |
| 39 | |
| 40 | #ifdef SC520_CDP_DEBUG |
| 41 | #define PRINTF(fmt,args...) printf (fmt ,##args) |
| 42 | #else |
| 43 | #define PRINTF(fmt,args...) |
| 44 | #endif |
| 45 | |
| 46 | unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; |
| 47 | |
Graeme Russ | 052bae1 | 2010-04-24 00:05:58 +1000 | [diff] [blame] | 48 | static void enet_timer_isr(void); |
| 49 | static void enet_toggle_run_led(void); |
| 50 | |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 51 | void init_sc520_enet (void) |
| 52 | { |
| 53 | /* Set CPU Speed to 100MHz */ |
Graeme Russ | 0c5ced7 | 2010-04-24 00:05:37 +1000 | [diff] [blame] | 54 | writeb(0x01, &sc520_mmcr->cpuctl); |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 55 | |
| 56 | /* wait at least one millisecond */ |
| 57 | asm("movl $0x2000,%%ecx\n" |
Graeme Russ | de7f938 | 2009-08-23 12:59:46 +1000 | [diff] [blame] | 58 | "0: pushl %%ecx\n" |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 59 | "popl %%ecx\n" |
Graeme Russ | de7f938 | 2009-08-23 12:59:46 +1000 | [diff] [blame] | 60 | "loop 0b\n": : : "ecx"); |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 61 | |
| 62 | /* turn on the SDRAM write buffer */ |
Graeme Russ | 0c5ced7 | 2010-04-24 00:05:37 +1000 | [diff] [blame] | 63 | writeb(0x11, &sc520_mmcr->dbctl); |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 64 | |
| 65 | /* turn on the cache and disable write through */ |
| 66 | asm("movl %%cr0, %%eax\n" |
| 67 | "andl $0x9fffffff, %%eax\n" |
| 68 | "movl %%eax, %%cr0\n" : : : "eax"); |
| 69 | } |
| 70 | |
| 71 | /* |
| 72 | * Miscellaneous platform dependent initializations |
| 73 | */ |
Graeme Russ | 078395c | 2009-11-24 20:04:21 +1100 | [diff] [blame] | 74 | int board_early_init_f(void) |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 75 | { |
| 76 | init_sc520_enet(); |
| 77 | |
Graeme Russ | 0c5ced7 | 2010-04-24 00:05:37 +1000 | [diff] [blame] | 78 | writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */ |
| 79 | writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */ |
| 80 | writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */ |
| 81 | writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */ |
| 82 | writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */ |
| 83 | writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */ |
| 84 | writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */ |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 85 | |
Graeme Russ | 0c5ced7 | 2010-04-24 00:05:37 +1000 | [diff] [blame] | 86 | writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */ |
| 87 | writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */ |
| 88 | writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */ |
| 89 | writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */ |
| 90 | writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */ |
| 91 | writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */ |
| 92 | writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */ |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 93 | |
Graeme Russ | 0c5ced7 | 2010-04-24 00:05:37 +1000 | [diff] [blame] | 94 | writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ |
| 95 | writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ |
| 96 | writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ |
| 97 | writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ |
| 98 | writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */ |
| 99 | writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ |
| 100 | writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ |
| 101 | writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */ |
| 102 | writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */ |
| 103 | writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */ |
| 104 | writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */ |
| 105 | writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */ |
| 106 | /* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */ |
| 107 | /* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 108 | |
| 109 | /* Disable Watchdog */ |
Graeme Russ | 0c5ced7 | 2010-04-24 00:05:37 +1000 | [diff] [blame] | 110 | writew(0x3333, &sc520_mmcr->wdtmrctl); |
| 111 | writew(0xcccc, &sc520_mmcr->wdtmrctl); |
| 112 | writew(0x0000, &sc520_mmcr->wdtmrctl); |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 113 | |
| 114 | /* Chip Select Configuration */ |
Graeme Russ | 0c5ced7 | 2010-04-24 00:05:37 +1000 | [diff] [blame] | 115 | writew(0x0033, &sc520_mmcr->bootcsctl); |
| 116 | writew(0x0615, &sc520_mmcr->romcs1ctl); |
| 117 | writew(0x0615, &sc520_mmcr->romcs2ctl); |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 118 | |
Graeme Russ | 06dfe37 | 2010-04-24 00:05:47 +1000 | [diff] [blame] | 119 | writeb(0x00, &sc520_mmcr->adddecctl); |
Graeme Russ | 0c5ced7 | 2010-04-24 00:05:37 +1000 | [diff] [blame] | 120 | writeb(0x07, &sc520_mmcr->uart1ctl); |
Graeme Russ | 06dfe37 | 2010-04-24 00:05:47 +1000 | [diff] [blame] | 121 | writeb(0x07, &sc520_mmcr->uart2ctl); |
Graeme Russ | 0c5ced7 | 2010-04-24 00:05:37 +1000 | [diff] [blame] | 122 | writeb(0x06, &sc520_mmcr->sysarbctl); |
| 123 | writew(0x0003, &sc520_mmcr->sysarbmenb); |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 124 | |
Graeme Russ | 078395c | 2009-11-24 20:04:21 +1100 | [diff] [blame] | 125 | return 0; |
| 126 | } |
| 127 | |
| 128 | int board_early_init_r(void) |
| 129 | { |
| 130 | /* CPU Speed to 100MHz */ |
| 131 | gd->cpu_clk = 100000000; |
| 132 | |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 133 | /* Crystal is 33.000MHz */ |
| 134 | gd->bus_clk = 33000000; |
| 135 | |
| 136 | return 0; |
| 137 | } |
| 138 | |
| 139 | int dram_init(void) |
| 140 | { |
| 141 | init_sc520_dram(); |
| 142 | return 0; |
| 143 | } |
| 144 | |
| 145 | void show_boot_progress(int val) |
| 146 | { |
| 147 | uchar led_mask; |
| 148 | |
| 149 | led_mask = 0x00; |
| 150 | |
| 151 | if (val < 0) |
| 152 | led_mask |= LED_ERR_BITMASK; |
| 153 | |
| 154 | led_mask |= (uchar)(val & 0x001f); |
| 155 | outb(led_mask, LED_LATCH_ADDRESS); |
| 156 | } |
| 157 | |
| 158 | |
| 159 | int last_stage_init(void) |
| 160 | { |
| 161 | int minor; |
| 162 | int major; |
| 163 | |
| 164 | major = minor = 0; |
| 165 | |
Graeme Russ | 052bae1 | 2010-04-24 00:05:58 +1000 | [diff] [blame] | 166 | outb(0x00, LED_LATCH_ADDRESS); |
| 167 | |
| 168 | register_timer_isr (enet_timer_isr); |
| 169 | |
Graeme Russ | e56d397 | 2008-12-07 10:28:57 +1100 | [diff] [blame] | 170 | printf("Serck Controls eNET\n"); |
| 171 | |
| 172 | return 0; |
| 173 | } |
| 174 | |
| 175 | ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) |
| 176 | { |
| 177 | if (banknum == 0) { /* non-CFI boot flash */ |
| 178 | info->portwidth = FLASH_CFI_8BIT; |
| 179 | info->chipwidth = FLASH_CFI_BY8; |
| 180 | info->interface = FLASH_CFI_X8; |
| 181 | return 1; |
| 182 | } else |
| 183 | return 0; |
| 184 | } |
Graeme Russ | a1eeccf | 2010-04-24 00:05:55 +1000 | [diff] [blame] | 185 | |
| 186 | int board_eth_init(bd_t *bis) |
| 187 | { |
| 188 | return pci_eth_init(bis); |
| 189 | } |
Graeme Russ | 1aa9195 | 2010-04-24 00:05:56 +1000 | [diff] [blame] | 190 | |
| 191 | void setup_pcat_compatibility() |
| 192 | { |
| 193 | /* disable global interrupt mode */ |
| 194 | writeb(0x40, &sc520_mmcr->picicr); |
| 195 | |
| 196 | /* set all irqs to edge */ |
| 197 | writeb(0x00, &sc520_mmcr->pic_mode[0]); |
| 198 | writeb(0x00, &sc520_mmcr->pic_mode[1]); |
| 199 | writeb(0x00, &sc520_mmcr->pic_mode[2]); |
| 200 | |
| 201 | /* |
| 202 | * active low polarity on PIC interrupt pins, |
| 203 | * active high polarity on all other irq pins |
| 204 | */ |
| 205 | writew(0x0000,&sc520_mmcr->intpinpol); |
| 206 | |
| 207 | /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */ |
| 208 | writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]); |
| 209 | writeb(SC520_IRQ8, &sc520_mmcr->rtcmap); |
| 210 | writeb(SC520_IRQ13, &sc520_mmcr->ferrmap); |
| 211 | |
| 212 | /* Disable all other interrupt sources */ |
| 213 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]); |
| 214 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]); |
| 215 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]); |
| 216 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]); |
| 217 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]); |
| 218 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */ |
| 219 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */ |
| 220 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */ |
| 221 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */ |
| 222 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */ |
| 223 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap); |
| 224 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap); |
| 225 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap); |
| 226 | writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap); |
| 227 | } |
Graeme Russ | 052bae1 | 2010-04-24 00:05:58 +1000 | [diff] [blame] | 228 | |
| 229 | void enet_timer_isr(void) |
| 230 | { |
| 231 | static long enet_ticks = 0; |
| 232 | |
| 233 | enet_ticks++; |
| 234 | |
| 235 | /* Toggle Watchdog every 100ms */ |
| 236 | if ((enet_ticks % 100) == 0) |
| 237 | hw_watchdog_reset(); |
| 238 | |
| 239 | /* Toggle Run LED every 500ms */ |
| 240 | if ((enet_ticks % 500) == 0) |
| 241 | enet_toggle_run_led(); |
| 242 | } |
| 243 | |
| 244 | void hw_watchdog_reset(void) |
| 245 | { |
| 246 | /* Watchdog Reset must be atomic */ |
| 247 | long flag = disable_interrupts(); |
| 248 | |
| 249 | if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT) |
| 250 | sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT; |
| 251 | else |
| 252 | sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT; |
| 253 | |
| 254 | if (flag) |
| 255 | enable_interrupts(); |
| 256 | } |
| 257 | |
| 258 | void enet_toggle_run_led(void) |
| 259 | { |
| 260 | unsigned char leds_state= inb(LED_LATCH_ADDRESS); |
| 261 | if (leds_state & LED_RUN_BITMASK) |
| 262 | outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS); |
| 263 | else |
| 264 | outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS); |
| 265 | } |