Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 0d1b83e553548c06df1e3ae76e6ea70681e0d347 / . / arch / arm / dts / imx93.dtsi
blob: 28026ccecc80f9ce5521951d20724a86393d22d8 [file] [log] [blame]
Peng Fan6b262d42022-07-26 16:41:09 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 NXP
4 */
5
6#include <dt-bindings/clock/imx93-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/thermal/thermal.h>
11#include <dt-bindings/power/imx93-power.h>
12#include <dt-bindings/usb/pd.h>
13
14#include "imx93-pinfunc.h"
15
16/ {
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 mmc0 = &usdhc1;
27 mmc1 = &usdhc2;
28 mmc2 = &usdhc3;
29 ethernet0 = &fec;
30 ethernet1 = &eqos;
31 serial0 = &lpuart1;
32 serial1 = &lpuart2;
33 serial2 = &lpuart3;
34 serial3 = &lpuart4;
35 serial4 = &lpuart5;
36 serial5 = &lpuart6;
37 serial6 = &lpuart7;
38 serial7 = &lpuart8;
39 i2c0 = &lpi2c1;
40 i2c1 = &lpi2c2;
41 i2c2 = &lpi2c3;
42 i2c3 = &lpi2c4;
43 i2c4 = &lpi2c5;
44 i2c5 = &lpi2c6;
45 usb0 = &usbotg1;
46 usb1 = &usbotg2;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 A55_0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a55";
56 reg = <0x0>;
57 enable-method = "psci";
58 #cooling-cells = <2>;
59 };
60
61 A55_1: cpu@100 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a55";
64 reg = <0x100>;
65 enable-method = "psci";
66 #cooling-cells = <2>;
67 };
68
69 };
70
71 osc_32k: clock-osc-32k {
72 compatible = "fixed-clock";
73 #clock-cells = <0>;
74 clock-frequency = <32768>;
75 clock-output-names = "osc_32k";
76 };
77
78 osc_24m: clock-osc-24m {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <24000000>;
82 clock-output-names = "osc_24m";
83 };
84
85 clk_ext1: clock-ext1 {
86 compatible = "fixed-clock";
87 #clock-cells = <0>;
88 clock-frequency = <133000000>;
89 clock-output-names = "clk_ext1";
90 };
91
92 psci {
93 compatible = "arm,psci-1.0";
94 method = "smc";
95 };
96
97 timer {
98 compatible = "arm,armv8-timer";
99 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
103 clock-frequency = <24000000>;
104 arm,no-tick-in-suspend;
105 interrupt-parent = <&gic>;
106 };
107
108 gic: interrupt-controller@48000000 {
109 compatible = "arm,gic-v3";
110 reg = <0 0x48000000 0 0x10000>,
111 <0 0x48040000 0 0xc0000>;
112 #interrupt-cells = <3>;
113 interrupt-controller;
114 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
115 interrupt-parent = <&gic>;
116 };
117
118 soc@0 {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges = <0x0 0x0 0x0 0x80000000>,
123 <0x28000000 0x0 0x28000000 0x10000000>;
124
125 aips1: bus@44000000 {
126 compatible = "fsl,aips-bus", "simple-bus";
127 reg = <0x44000000 0x800000>;
128 #address-cells = <1>;
129 #size-cells = <1>;
130 ranges;
131
132 mu1: mailbox@44230000 {
133 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
134 reg = <0x44230000 0x10000>;
135 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
136 #mbox-cells = <2>;
137 status = "disabled";
138 };
139
140 anomix_ns_gpr: blk-ctrl-anomix@42420000 {
141 compatible = "syscon";
142 reg = <0x44210000 0x1000>;
143 };
144
145 system_counter: timer@44290000 {
146 compatible = "nxp,sysctr-timer";
147 reg = <0x44290000 0x30000>;
148 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
149 clocks = <&osc_24m>;
150 clock-names = "per";
151 };
152
153 i3c1: i3c-master@44330000 {
154 #address-cells = <3>;
155 #size-cells = <0>;
156 compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
157 reg = <0x44330000 0x10000>;
158 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&clk IMX93_CLK_I3C1_GATE>,
160 <&clk IMX93_CLK_I3C1_GATE>,
161 <&clk IMX93_CLK_DUMMY>;
162 clock-names = "pclk", "fast_clk", "slow_clk";
163 status = "disabled";
164 };
165
166 lpi2c1: i2c@44340000 {
167 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
168 reg = <0x44340000 0x10000>;
169 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
171 <&clk IMX93_CLK_LPI2C1_GATE>;
172 clock-names = "per", "ipg";
173 status = "disabled";
174 };
175
176 lpi2c2: i2c@44350000 {
177 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
178 reg = <0x44350000 0x10000>;
179 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
181 <&clk IMX93_CLK_LPI2C2_GATE>;
182 clock-names = "per", "ipg";
183 status = "disabled";
184 };
185
186 lpspi1: spi@44360000 {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
190 reg = <0x44360000 0x10000>;
191 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
193 <&clk IMX93_CLK_LPSPI1_GATE>;
194 clock-names = "per", "ipg";
195 status = "disabled";
196 };
197
198 lpspi2: spi@44370000 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
202 reg = <0x44370000 0x10000>;
203 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
205 <&clk IMX93_CLK_LPSPI2_GATE>;
206 clock-names = "per", "ipg";
207 status = "disabled";
208 };
209
210 lpuart1: serial@44380000 {
211 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
212 "fsl,imx7ulp-lpuart";
213 reg = <0x44380000 0x1000>;
214 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&clk IMX93_CLK_LPUART1_GATE>;
216 clock-names = "ipg";
217 status = "disabled";
218 };
219
220 lpuart2: serial@44390000 {
221 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
222 "fsl,imx7ulp-lpuart";
223 reg = <0x44390000 0x1000>;
224 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&clk IMX93_CLK_LPUART2_GATE>;
226 clock-names = "ipg";
227 status = "disabled";
228 };
229
230 iomuxc: pinctrl@443c0000 {
231 compatible = "fsl,imx93-iomuxc";
232 reg = <0x443c0000 0x10000>;
233 };
234
235 clk: clock-controller@44450000 {
236 compatible = "fsl,imx93-ccm";
237 reg = <0x44450000 0x10000>;
238 #clock-cells = <1>;
239 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
240 clock-names = "osc_32k", "osc_24m", "clk_ext1";
241 assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
242 assigned-clock-rates = <393216000>;
243 status = "okay";
244 };
245
246 anatop: anatop@44480000 {
247 compatible = "fsl,imx93-anatop", "syscon";
248 reg = <0x44480000 0x10000>;
249 };
250
251 adc1: adc@44530000 {
252 compatible = "nxp,imx93-adc";
253 reg = <0x44530000 0x10000>;
254 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clk IMX93_CLK_ADC1_GATE>;
259 clock-names = "ipg";
260 status = "disabled";
261 };
262 };
263
264 aips2: bus@42000000 {
265 compatible = "fsl,aips-bus", "simple-bus";
266 reg = <0x42000000 0x800000>;
267 #address-cells = <1>;
268 #size-cells = <1>;
269 ranges;
270
271 wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 {
272 compatible = "syscon";
273 reg = <0x42420000 0x1000>;
274 };
275
276 mu2: mailbox@42440000 {
277 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
278 reg = <0x42440000 0x10000>;
279 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
280 #mbox-cells = <2>;
281 status = "disabled";
282 };
283
284 wdog3: wdog@42490000 {
285 compatible = "fsl,imx93-wdt";
286 reg = <0x42490000 0x10000>;
287 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clk IMX93_CLK_WDOG3_GATE>;
289 timeout-sec = <40>;
290 status = "disabled";
291 };
292
293 tpm4: pwm@424f0000 {
294 compatible = "fsl,imx7ulp-pwm";
295 reg = <0x424f0000 0x1000>;
296 clocks = <&clk IMX93_CLK_TPM4_GATE>;
297 assigned-clocks = <&clk IMX93_CLK_TPM4>;
298 assigned-clock-parents = <&clk IMX93_CLK_24M>;
299 assigned-clock-rates = <24000000>;
300 #pwm-cells = <3>;
301 status = "disabled";
302 };
303
304 i3c2: i3c-master@42520000 {
305 #address-cells = <3>;
306 #size-cells = <0>;
307 compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
308 reg = <0x42520000 0x10000>;
309 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clk IMX93_CLK_I3C2_GATE>,
311 <&clk IMX93_CLK_I3C2_GATE>,
312 <&clk IMX93_CLK_DUMMY>;
313 clock-names = "pclk", "fast_clk", "slow_clk";
314 status = "disabled";
315 };
316
317 lpi2c3: i2c@42530000 {
318 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
319 reg = <0x42530000 0x10000>;
320 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
322 <&clk IMX93_CLK_LPI2C3_GATE>;
323 clock-names = "per", "ipg";
324 status = "disabled";
325 };
326
327 lpi2c4: i2c@42540000 {
328 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
329 reg = <0x42540000 0x10000>;
330 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
332 <&clk IMX93_CLK_LPI2C4_GATE>;
333 clock-names = "per", "ipg";
334 status = "disabled";
335 };
336
337 lpspi3: spi@42550000 {
338 #address-cells = <1>;
339 #size-cells = <0>;
340 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
341 reg = <0x42550000 0x10000>;
342 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
344 <&clk IMX93_CLK_LPSPI3_GATE>;
345 clock-names = "per", "ipg";
346 status = "disabled";
347 };
348
349 lpspi4: spi@42560000 {
350 #address-cells = <1>;
351 #size-cells = <0>;
352 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
353 reg = <0x42560000 0x10000>;
354 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
356 <&clk IMX93_CLK_LPSPI4_GATE>;
357 clock-names = "per", "ipg";
358 status = "disabled";
359 };
360
361 lpuart3: serial@42570000 {
362 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
363 "fsl,imx7ulp-lpuart";
364 reg = <0x42570000 0x1000>;
365 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clk IMX93_CLK_LPUART3_GATE>;
367 clock-names = "ipg";
368 status = "disabled";
369 };
370
371 lpuart4: serial@42580000 {
372 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
373 "fsl,imx7ulp-lpuart";
374 reg = <0x42580000 0x1000>;
375 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clk IMX93_CLK_LPUART4_GATE>;
377 clock-names = "ipg";
378 status = "disabled";
379 };
380
381 lpuart5: serial@42590000 {
382 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
383 "fsl,imx7ulp-lpuart";
384 reg = <0x42590000 0x1000>;
385 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&clk IMX93_CLK_LPUART5_GATE>;
387 clock-names = "ipg";
388 status = "disabled";
389 };
390
391 lpuart6: serial@425a0000 {
392 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
393 "fsl,imx7ulp-lpuart";
394 reg = <0x425a0000 0x1000>;
395 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&clk IMX93_CLK_LPUART6_GATE>;
397 clock-names = "ipg";
398 status = "disabled";
399 };
400
401 flexspi: spi@425e0000 {
402 #address-cells = <1>;
403 #size-cells = <0>;
404 compatible = "nxp,imx8mm-fspi";
405 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
406 reg-names = "fspi_base", "fspi_mmap";
407 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&clk IMX93_CLK_DUMMY>,
409 <&clk IMX93_CLK_DUMMY>;
410 clock-names = "fspi", "fspi_en";
411 status = "disabled";
412 };
413
414 lpuart7: serial@42690000 {
415 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
416 "fsl,imx7ulp-lpuart";
417 reg = <0x42690000 0x1000>;
418 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clk IMX93_CLK_LPUART7_GATE>;
420 clock-names = "ipg";
421 status = "disabled";
422 };
423
424 lpuart8: serial@426a0000 {
425 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
426 "fsl,imx7ulp-lpuart";
427 reg = <0x426a0000 0x1000>;
428 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&clk IMX93_CLK_LPUART8_GATE>;
430 clock-names = "ipg";
431 status = "disabled";
432 };
433
434 lpi2c5: i2c@426b0000 {
435 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
436 reg = <0x426b0000 0x10000>;
437 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
439 <&clk IMX93_CLK_LPI2C5_GATE>;
440 clock-names = "per", "ipg";
441 status = "disabled";
442 };
443
444 lpi2c6: i2c@426c0000 {
445 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
446 reg = <0x426c0000 0x10000>;
447 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
449 <&clk IMX93_CLK_LPI2C6_GATE>;
450 clock-names = "per", "ipg";
451 status = "disabled";
452 };
453 };
454
455 aips3: bus@42800000 {
456 compatible = "fsl,aips-bus", "simple-bus";
457 reg = <0x42800000 0x800000>;
458 #address-cells = <1>;
459 #size-cells = <1>;
460 ranges;
461
462 usdhc1: mmc@42850000 {
463 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
464 reg = <0x42850000 0x10000>;
465 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clk IMX93_CLK_DUMMY>,
467 <&clk IMX93_CLK_DUMMY>,
468 <&clk IMX93_CLK_USDHC1_GATE>;
469 clock-names = "ipg", "ahb", "per";
470 bus-width = <8>;
471 fsl,tuning-start-tap = <20>;
472 fsl,tuning-step= <2>;
473 status = "disabled";
474 };
475
476 usdhc2: mmc@42860000 {
477 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
478 reg = <0x42860000 0x10000>;
479 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&clk IMX93_CLK_DUMMY>,
481 <&clk IMX93_CLK_DUMMY>,
482 <&clk IMX93_CLK_USDHC2_GATE>;
483 clock-names = "ipg", "ahb", "per";
484 bus-width = <4>;
485 fsl,tuning-start-tap = <20>;
486 fsl,tuning-step= <2>;
487 status = "disabled";
488 };
489
490 fec: ethernet@42890000 {
491 compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec";
492 reg = <0x42890000 0x10000>;
493 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
498 <&clk IMX93_CLK_WAKEUP_AXI>,
499 <&clk IMX93_CLK_ENET_TIMER1>,
500 <&clk IMX93_CLK_ENET_REF>,
501 <&clk IMX93_CLK_ENET_REF_PHY>;
502 clock-names = "ipg", "ahb", "ptp",
503 "enet_clk_ref", "enet_out";
504 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
505 <&clk IMX93_CLK_ENET_REF>,
506 <&clk IMX93_CLK_ENET_REF_PHY>;
507 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
508 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
509 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
510 assigned-clock-rates = <100000000>, <250000000>, <50000000>;
511 fsl,num-tx-queues = <3>;
512 fsl,num-rx-queues = <3>;
513 fsl,wakeup_irq = <2>;
514 status = "disabled";
515 };
516
517 eqos: ethernet@428a0000 {
518 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
519 reg = <0x428a0000 0x10000>;
520 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
522 interrupt-names = "eth_wake_irq", "macirq";
523 clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
524 <&clk IMX93_CLK_WAKEUP_AXI>,
525 <&clk IMX93_CLK_ENET_TIMER2>,
526 <&clk IMX93_CLK_ENET>,
527 <&clk IMX93_CLK_WAKEUP_AXI>;
528 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
529 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
530 <&clk IMX93_CLK_ENET>;
531 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
532 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
533 assigned-clock-rates = <100000000>, <250000000>;
534 intf_mode = <&wakeupmix_gpr 0x28>;
535 clk_csr = <0>;
536 status = "disabled";
537 };
538
539 usdhc3: mmc@428b0000 {
540 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
541 reg = <0x428b0000 0x10000>;
542 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&clk IMX93_CLK_DUMMY>,
544 <&clk IMX93_CLK_DUMMY>,
545 <&clk IMX93_CLK_USDHC3_GATE>;
546 clock-names = "ipg", "ahb", "per";
547 bus-width = <4>;
548 fsl,tuning-start-tap = <20>;
549 fsl,tuning-step= <2>;
550 status = "disabled";
551 };
552 };
553
554 gpio2: gpio@43810000 {
555 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
556 reg = <0x43810080 0x1000>, <0x43810040 0x40>;
557 gpio-controller;
558 #gpio-cells = <2>;
559 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
561 interrupt-controller;
562 #interrupt-cells = <2>;
563 gpio-ranges = <&iomuxc 0 32 32>;
564 };
565
566 gpio3: gpio@43820000 {
567 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
568 reg = <0x43820080 0x1000>, <0x43820040 0x40>;
569 gpio-controller;
570 #gpio-cells = <2>;
571 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 gpio-ranges = <&iomuxc 0 64 32>;
576 };
577
578 gpio4: gpio@43830000 {
579 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
580 reg = <0x43830080 0x1000>, <0x43830040 0x40>;
581 gpio-controller;
582 #gpio-cells = <2>;
583 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
585 interrupt-controller;
586 #interrupt-cells = <2>;
587 gpio-ranges = <&iomuxc 0 96 32>;
588 };
589
590 gpio1: gpio@47400000 {
591 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
592 reg = <0x47400080 0x1000>, <0x47400040 0x40>;
593 gpio-controller;
594 #gpio-cells = <2>;
595 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 gpio-ranges = <&iomuxc 0 0 32>;
600 };
601
602 ocotp: efuse@47510000 {
603 #address-cells = <1>;
604 #size-cells = <1>;
605 compatible = "fsl,imx93-ocotp", "syscon";
606 reg = <0x47510000 0x1000>;
607 status = "disabled";
608 };
609
610 s4muap: s4muap@47520000 {
611 compatible = "fsl,imx93-mu-s4";
612 reg = <0x47520000 0x10000>;
613 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-names = "txirq", "rxirq";
616 #mbox-cells = <2>;
617 status = "okay";
618 };
619
620 sentnl_mu: sentnl-mu {
621 #address-cells = <1>;
622 #size-cells = <1>;
623 compatible = "fsl,imx-sentnl";
624 mboxes = <&s4muap 0 0 &s4muap 1 0>;
625 mbox-names = "tx", "rx";
626 fsl,sentnl_mu_id = <2>;
627 fsl,sentnl_mu_max_users = <4>;
628 status = "okay";
629 dma-ranges = <0x80000000 0x80000000 0x20000000>;
630 };
631
632 ddr-pmu@4e300e00 {
633 compatible = "fsl,imx93-ddr-pmu";
634 reg = <0x4e300dc0 0x200>; /* _dc0 ~ _eb8 */
635 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
636 };
637
638 usbphynop1: usbphynop1 {
639 compatible = "usb-nop-xceiv";
640 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
641 clock-names = "main_clk";
642 };
643
644 usbotg1: usb@4c100000 {
645 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
646 reg = <0x4c100000 0x200>;
647 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
649 clock-names = "usb1_ctrl_root_clk";
650 assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
651 assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
652 fsl,usbphy = <&usbphynop1>;
653 fsl,usbmisc = <&usbmisc1 0>;
654 status = "disabled";
655 };
656
657 usbmisc1: usbmisc@4c100200 {
658 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
659 #index-cells = <1>;
660 reg = <0x4c100200 0x200>;
661 };
662
663 usbphynop2: usbphynop2 {
664 compatible = "usb-nop-xceiv";
665 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
666 clock-names = "main_clk";
667 };
668
669 usbotg2: usb@4c200000 {
670 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
671 reg = <0x4c200000 0x200>;
672 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
674 clock-names = "usb2_ctrl_root_clk";
675 assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
676 assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
677 fsl,usbphy = <&usbphynop2>;
678 fsl,usbmisc = <&usbmisc2 0>;
679 status = "disabled";
680 };
681
682 usbmisc2: usbmisc@4c200200 {
683 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
684 #index-cells = <1>;
685 reg = <0x4c200200 0x200>;
686 };
687 };
688};