Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> |
| 3 | * |
| 4 | * (C) Copyright 2009 Freescale Semiconductor, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #include <config.h> |
| 23 | #include <asm/arch/imx-regs.h> |
Stefano Babic | 2a1f1ac | 2011-09-05 04:32:28 +0000 | [diff] [blame] | 24 | #include <generated/asm-offsets.h> |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 25 | |
| 26 | /* |
| 27 | * L2CC Cache setup/invalidation/disable |
| 28 | */ |
| 29 | .macro init_l2cc |
| 30 | /* explicitly disable L2 cache */ |
| 31 | mrc 15, 0, r0, c1, c0, 1 |
| 32 | bic r0, r0, #0x2 |
| 33 | mcr 15, 0, r0, c1, c0, 1 |
| 34 | |
| 35 | /* reconfigure L2 cache aux control reg */ |
Wolfgang Denk | a2cfb24 | 2010-03-12 23:06:04 +0100 | [diff] [blame] | 36 | mov r0, #0xC0 /* tag RAM */ |
| 37 | add r0, r0, #0x4 /* data RAM */ |
| 38 | orr r0, r0, #(1 << 24) /* disable write allocate delay */ |
| 39 | orr r0, r0, #(1 << 23) /* disable write allocate combine */ |
| 40 | orr r0, r0, #(1 << 22) /* disable write allocate */ |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 41 | |
David Jander | dd6f787 | 2011-07-14 03:58:57 +0000 | [diff] [blame] | 42 | #if defined(CONFIG_MX51) |
| 43 | ldr r1, =0x0 |
| 44 | ldr r3, [r1, #ROM_SI_REV] |
| 45 | cmp r3, #0x10 |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 46 | |
| 47 | /* disable write combine for TO 2 and lower revs */ |
| 48 | orrls r0, r0, #(1 << 25) |
David Jander | dd6f787 | 2011-07-14 03:58:57 +0000 | [diff] [blame] | 49 | #endif |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 50 | |
| 51 | mcr 15, 1, r0, c9, c0, 2 |
| 52 | .endm /* init_l2cc */ |
| 53 | |
| 54 | /* AIPS setup - Only setup MPROTx registers. |
| 55 | * The PACR default values are good.*/ |
| 56 | .macro init_aips |
| 57 | /* |
| 58 | * Set all MPROTx to be non-bufferable, trusted for R/W, |
| 59 | * not forced to user-mode. |
| 60 | */ |
| 61 | ldr r0, =AIPS1_BASE_ADDR |
| 62 | ldr r1, =0x77777777 |
| 63 | str r1, [r0, #0x0] |
| 64 | str r1, [r0, #0x4] |
| 65 | ldr r0, =AIPS2_BASE_ADDR |
| 66 | str r1, [r0, #0x0] |
| 67 | str r1, [r0, #0x4] |
| 68 | /* |
| 69 | * Clear the on and off peripheral modules Supervisor Protect bit |
| 70 | * for SDMA to access them. Did not change the AIPS control registers |
| 71 | * (offset 0x20) access type |
| 72 | */ |
| 73 | .endm /* init_aips */ |
| 74 | |
| 75 | /* M4IF setup */ |
| 76 | .macro init_m4if |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 77 | #ifdef CONFIG_MX51 |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 78 | /* VPU and IPU given higher priority (0x4) |
| 79 | * IPU accesses with ID=0x1 given highest priority (=0xA) |
| 80 | */ |
| 81 | ldr r0, =M4IF_BASE_ADDR |
| 82 | |
| 83 | ldr r1, =0x00000203 |
| 84 | str r1, [r0, #0x40] |
| 85 | |
| 86 | ldr r1, =0x0 |
| 87 | str r1, [r0, #0x44] |
| 88 | |
| 89 | ldr r1, =0x00120125 |
| 90 | str r1, [r0, #0x9C] |
| 91 | |
| 92 | ldr r1, =0x001901A3 |
| 93 | str r1, [r0, #0x48] |
| 94 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 95 | #endif |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 96 | .endm /* init_m4if */ |
| 97 | |
| 98 | .macro setup_pll pll, freq |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 99 | ldr r0, =\pll |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 100 | ldr r1, =0x00001232 |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 101 | str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 102 | mov r1, #0x2 |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 103 | str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 104 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 105 | ldr r1, W_DP_OP_\freq |
| 106 | str r1, [r0, #PLL_DP_OP] |
| 107 | str r1, [r0, #PLL_DP_HFS_OP] |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 108 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 109 | ldr r1, W_DP_MFD_\freq |
| 110 | str r1, [r0, #PLL_DP_MFD] |
| 111 | str r1, [r0, #PLL_DP_HFS_MFD] |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 112 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 113 | ldr r1, W_DP_MFN_\freq |
| 114 | str r1, [r0, #PLL_DP_MFN] |
| 115 | str r1, [r0, #PLL_DP_HFS_MFN] |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 116 | |
| 117 | ldr r1, =0x00001232 |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 118 | str r1, [r0, #PLL_DP_CTL] |
| 119 | 1: ldr r1, [r0, #PLL_DP_CTL] |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 120 | ands r1, r1, #0x1 |
| 121 | beq 1b |
| 122 | .endm |
| 123 | |
David Jander | 088b338 | 2011-07-13 21:11:53 +0000 | [diff] [blame] | 124 | .macro setup_pll_errata pll, freq |
| 125 | ldr r2, =\pll |
| 126 | mov r1, #0x0 |
| 127 | str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */ |
| 128 | ldr r1, =0x00001236 |
| 129 | str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */ |
| 130 | 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */ |
| 131 | ands r1, r1, #0x1 |
| 132 | beq 1b |
| 133 | |
| 134 | ldr r5, \freq |
| 135 | str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */ |
| 136 | str r5, [r2, #PLL_DP_HFS_MFN] |
| 137 | |
| 138 | mov r1, #0x1 |
| 139 | str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */ |
| 140 | |
| 141 | 2: ldr r1, [r2, #PLL_DP_CONFIG] |
| 142 | tst r1, #1 |
| 143 | bne 2b |
| 144 | |
| 145 | ldr r1, =100 /* Wait at least 4 us */ |
| 146 | 3: subs r1, r1, #1 |
| 147 | bge 3b |
| 148 | |
| 149 | mov r1, #0x2 |
| 150 | str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ |
| 151 | .endm |
| 152 | |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 153 | .macro init_clock |
| 154 | ldr r0, =CCM_BASE_ADDR |
| 155 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 156 | #if defined(CONFIG_MX51) |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 157 | /* Gate of clocks to the peripherals first */ |
| 158 | ldr r1, =0x3FFFFFFF |
| 159 | str r1, [r0, #CLKCTL_CCGR0] |
| 160 | ldr r1, =0x0 |
| 161 | str r1, [r0, #CLKCTL_CCGR1] |
| 162 | str r1, [r0, #CLKCTL_CCGR2] |
| 163 | str r1, [r0, #CLKCTL_CCGR3] |
| 164 | |
| 165 | ldr r1, =0x00030000 |
| 166 | str r1, [r0, #CLKCTL_CCGR4] |
| 167 | ldr r1, =0x00FFF030 |
| 168 | str r1, [r0, #CLKCTL_CCGR5] |
| 169 | ldr r1, =0x00000300 |
| 170 | str r1, [r0, #CLKCTL_CCGR6] |
| 171 | |
| 172 | /* Disable IPU and HSC dividers */ |
| 173 | mov r1, #0x60000 |
| 174 | str r1, [r0, #CLKCTL_CCDR] |
| 175 | |
| 176 | /* Make sure to switch the DDR away from PLL 1 */ |
| 177 | ldr r1, =0x19239145 |
| 178 | str r1, [r0, #CLKCTL_CBCDR] |
| 179 | /* make sure divider effective */ |
| 180 | 1: ldr r1, [r0, #CLKCTL_CDHIPR] |
| 181 | cmp r1, #0x0 |
| 182 | bne 1b |
Fabio Estevam | d7deecf | 2011-10-24 08:08:00 +0000 | [diff] [blame] | 183 | #else |
| 184 | ldr r1, =0x3FFFFFFF |
| 185 | str r1, [r0, #CLKCTL_CCGR0] |
| 186 | ldr r1, =0x0 |
| 187 | str r1, [r0, #CLKCTL_CCGR1] |
| 188 | str r1, [r0, #CLKCTL_CCGR2] |
| 189 | str r1, [r0, #CLKCTL_CCGR3] |
| 190 | str r1, [r0, #CLKCTL_CCGR7] |
| 191 | |
| 192 | ldr r1, =0x00030000 |
| 193 | str r1, [r0, #CLKCTL_CCGR4] |
| 194 | ldr r1, =0x00FFF030 |
| 195 | str r1, [r0, #CLKCTL_CCGR5] |
| 196 | ldr r1, =0x0F00030F |
| 197 | str r1, [r0, #CLKCTL_CCGR6] |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 198 | #endif |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 199 | |
| 200 | /* Switch ARM to step clock */ |
| 201 | mov r1, #0x4 |
| 202 | str r1, [r0, #CLKCTL_CCSR] |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 203 | |
David Jander | 088b338 | 2011-07-13 21:11:53 +0000 | [diff] [blame] | 204 | #if defined(CONFIG_MX51_PLL_ERRATA) |
| 205 | setup_pll PLL1_BASE_ADDR, 864 |
| 206 | setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT |
| 207 | #else |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 208 | setup_pll PLL1_BASE_ADDR, 800 |
David Jander | 088b338 | 2011-07-13 21:11:53 +0000 | [diff] [blame] | 209 | #endif |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 210 | |
| 211 | #if defined(CONFIG_MX51) |
| 212 | setup_pll PLL3_BASE_ADDR, 665 |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 213 | |
| 214 | /* Switch peripheral to PLL 3 */ |
| 215 | ldr r0, =CCM_BASE_ADDR |
Wolfgang Denk | a2cfb24 | 2010-03-12 23:06:04 +0100 | [diff] [blame] | 216 | ldr r1, =0x000010C0 |
Stefano Babic | 0c3d8ee | 2010-03-28 13:43:26 +0200 | [diff] [blame] | 217 | orr r1,r1,#CONFIG_SYS_DDR_CLKSEL |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 218 | str r1, [r0, #CLKCTL_CBCMR] |
| 219 | ldr r1, =0x13239145 |
| 220 | str r1, [r0, #CLKCTL_CBCDR] |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 221 | setup_pll PLL2_BASE_ADDR, 665 |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 222 | |
| 223 | /* Switch peripheral to PLL2 */ |
| 224 | ldr r0, =CCM_BASE_ADDR |
| 225 | ldr r1, =0x19239145 |
| 226 | str r1, [r0, #CLKCTL_CBCDR] |
| 227 | ldr r1, =0x000020C0 |
Stefano Babic | 0c3d8ee | 2010-03-28 13:43:26 +0200 | [diff] [blame] | 228 | orr r1,r1,#CONFIG_SYS_DDR_CLKSEL |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 229 | str r1, [r0, #CLKCTL_CBCMR] |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 230 | #endif |
| 231 | setup_pll PLL3_BASE_ADDR, 216 |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 232 | |
| 233 | /* Set the platform clock dividers */ |
| 234 | ldr r0, =ARM_BASE_ADDR |
| 235 | ldr r1, =0x00000725 |
| 236 | str r1, [r0, #0x14] |
| 237 | |
| 238 | ldr r0, =CCM_BASE_ADDR |
| 239 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 240 | #if defined(CONFIG_MX51) |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 241 | /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ |
| 242 | ldr r1, =0x0 |
| 243 | ldr r3, [r1, #ROM_SI_REV] |
| 244 | cmp r3, #0x10 |
| 245 | movls r1, #0x1 |
| 246 | movhi r1, #0 |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 247 | #else |
| 248 | mov r1, #0 |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 249 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 250 | #endif |
| 251 | str r1, [r0, #CLKCTL_CACRR] |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 252 | /* Switch ARM back to PLL 1 */ |
| 253 | mov r1, #0 |
| 254 | str r1, [r0, #CLKCTL_CCSR] |
| 255 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 256 | #if defined(CONFIG_MX51) |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 257 | /* setup the rest */ |
| 258 | /* Use lp_apm (24MHz) source for perclk */ |
| 259 | ldr r1, =0x000020C2 |
Stefano Babic | 0c3d8ee | 2010-03-28 13:43:26 +0200 | [diff] [blame] | 260 | orr r1,r1,#CONFIG_SYS_DDR_CLKSEL |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 261 | str r1, [r0, #CLKCTL_CBCMR] |
| 262 | /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ |
Stefano Babic | 0c3d8ee | 2010-03-28 13:43:26 +0200 | [diff] [blame] | 263 | ldr r1, =CONFIG_SYS_CLKTL_CBCDR |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 264 | str r1, [r0, #CLKCTL_CBCDR] |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 265 | #endif |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 266 | |
| 267 | /* Restore the default values in the Gate registers */ |
| 268 | ldr r1, =0xFFFFFFFF |
| 269 | str r1, [r0, #CLKCTL_CCGR0] |
| 270 | str r1, [r0, #CLKCTL_CCGR1] |
| 271 | str r1, [r0, #CLKCTL_CCGR2] |
| 272 | str r1, [r0, #CLKCTL_CCGR3] |
| 273 | str r1, [r0, #CLKCTL_CCGR4] |
| 274 | str r1, [r0, #CLKCTL_CCGR5] |
| 275 | str r1, [r0, #CLKCTL_CCGR6] |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 276 | #if defined(CONFIG_MX53) |
| 277 | str r1, [r0, #CLKCTL_CCGR7] |
| 278 | #endif |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 279 | |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 280 | #if defined(CONFIG_MX51) |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 281 | /* Use PLL 2 for UART's, get 66.5MHz from it */ |
| 282 | ldr r1, =0xA5A2A020 |
| 283 | str r1, [r0, #CLKCTL_CSCMR1] |
| 284 | ldr r1, =0x00C30321 |
| 285 | str r1, [r0, #CLKCTL_CSCDR1] |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 286 | #elif defined(CONFIG_MX53) |
Fabio Estevam | 0d1ad1f | 2012-03-21 05:42:45 +0000 | [diff] [blame^] | 287 | /* Switch peripheral to PLL2 */ |
| 288 | ldr r0, =CCM_BASE_ADDR |
| 289 | ldr r1, =0x00808145 |
| 290 | orr r1, r1, #(2 << 10) |
| 291 | orr r1, r1, #(0 << 16) |
| 292 | orr r1, r1, #(1 << 19) |
| 293 | str r1, [r0, #CLKCTL_CBCDR] |
| 294 | |
| 295 | ldr r1, =0x00016154 |
| 296 | str r1, [r0, #CLKCTL_CBCMR] |
| 297 | /* Change uart clk parent to pll2*/ |
| 298 | ldr r1, [r0, #CLKCTL_CSCMR1] |
| 299 | and r1, r1, #0xfcffffff |
| 300 | orr r1, r1, #0x01000000 |
| 301 | str r1, [r0, #CLKCTL_CSCMR1] |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 302 | ldr r1, [r0, #CLKCTL_CSCDR1] |
Fabio Estevam | 0d1ad1f | 2012-03-21 05:42:45 +0000 | [diff] [blame^] | 303 | and r1, r1, #0xffffffc0 |
| 304 | orr r1, r1, #0x0a |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 305 | str r1, [r0, #CLKCTL_CSCDR1] |
| 306 | #endif |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 307 | /* make sure divider effective */ |
| 308 | 1: ldr r1, [r0, #CLKCTL_CDHIPR] |
| 309 | cmp r1, #0x0 |
| 310 | bne 1b |
| 311 | |
| 312 | mov r1, #0x0 |
| 313 | str r1, [r0, #CLKCTL_CCDR] |
| 314 | |
| 315 | /* for cko - for ARM div by 8 */ |
| 316 | mov r1, #0x000A0000 |
| 317 | add r1, r1, #0x00000F0 |
| 318 | str r1, [r0, #CLKCTL_CCOSR] |
| 319 | .endm |
| 320 | |
| 321 | .macro setup_wdog |
| 322 | ldr r0, =WDOG1_BASE_ADDR |
| 323 | mov r1, #0x30 |
| 324 | strh r1, [r0] |
| 325 | .endm |
| 326 | |
| 327 | .section ".text.init", "x" |
| 328 | |
| 329 | .globl lowlevel_init |
| 330 | lowlevel_init: |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 331 | #if defined(CONFIG_MX51) |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 332 | ldr r0, =GPIO1_BASE_ADDR |
| 333 | ldr r1, [r0, #0x0] |
| 334 | orr r1, r1, #(1 << 23) |
| 335 | str r1, [r0, #0x0] |
| 336 | ldr r1, [r0, #0x4] |
| 337 | orr r1, r1, #(1 << 23) |
| 338 | str r1, [r0, #0x4] |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 339 | #endif |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 340 | |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 341 | init_l2cc |
| 342 | |
| 343 | init_aips |
| 344 | |
| 345 | init_m4if |
| 346 | |
| 347 | init_clock |
| 348 | |
Stefano Babic | a521a77 | 2010-01-20 18:19:32 +0100 | [diff] [blame] | 349 | /* r12 saved upper lr*/ |
| 350 | mov pc,lr |
| 351 | |
| 352 | /* Board level setting value */ |
David Jander | 088b338 | 2011-07-13 21:11:53 +0000 | [diff] [blame] | 353 | W_DP_OP_864: .word DP_OP_864 |
| 354 | W_DP_MFD_864: .word DP_MFD_864 |
| 355 | W_DP_MFN_864: .word DP_MFN_864 |
| 356 | W_DP_MFN_800_DIT: .word DP_MFN_800_DIT |
Liu Hui-R64343 | baa2d78 | 2011-01-03 22:27:35 +0000 | [diff] [blame] | 357 | W_DP_OP_800: .word DP_OP_800 |
| 358 | W_DP_MFD_800: .word DP_MFD_800 |
| 359 | W_DP_MFN_800: .word DP_MFN_800 |
| 360 | W_DP_OP_665: .word DP_OP_665 |
| 361 | W_DP_MFD_665: .word DP_MFD_665 |
| 362 | W_DP_MFN_665: .word DP_MFN_665 |
| 363 | W_DP_OP_216: .word DP_OP_216 |
| 364 | W_DP_MFD_216: .word DP_MFD_216 |
| 365 | W_DP_MFN_216: .word DP_MFN_216 |