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git01.mediatek.com / filogic / uboot / 0d063f338ac660a007986af438eb8c64062ad88a / . / dts / upstream / src / arm64 / mediatek / mt2712e.dtsi
blob: 082672efba0a3408e9a9bb47ffad26046f97c3a2 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: YT Shen <yt.shen@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8#include <dt-bindings/clock/mt2712-clk.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/memory/mt2712-larb-port.h>
12#include <dt-bindings/phy/phy.h>
13#include <dt-bindings/power/mt2712-power.h>
14#include "mt2712-pinfunc.h"
15
16/ {
17 compatible = "mediatek,mt2712";
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cluster0_opp: opp-table-0 {
23 compatible = "operating-points-v2";
24 opp-shared;
25 opp00 {
26 opp-hz = /bits/ 64 <598000000>;
27 opp-microvolt = <1000000>;
28 };
29 opp01 {
30 opp-hz = /bits/ 64 <702000000>;
31 opp-microvolt = <1000000>;
32 };
33 opp02 {
34 opp-hz = /bits/ 64 <793000000>;
35 opp-microvolt = <1000000>;
36 };
37 };
38
39 cluster1_opp: opp-table-1 {
40 compatible = "operating-points-v2";
41 opp-shared;
42 opp00 {
43 opp-hz = /bits/ 64 <598000000>;
44 opp-microvolt = <1000000>;
45 };
46 opp01 {
47 opp-hz = /bits/ 64 <702000000>;
48 opp-microvolt = <1000000>;
49 };
50 opp02 {
51 opp-hz = /bits/ 64 <793000000>;
52 opp-microvolt = <1000000>;
53 };
54 opp03 {
55 opp-hz = /bits/ 64 <897000000>;
56 opp-microvolt = <1000000>;
57 };
58 opp04 {
59 opp-hz = /bits/ 64 <1001000000>;
60 opp-microvolt = <1000000>;
61 };
62 };
63
64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 cpu-map {
69 cluster0 {
70 core0 {
71 cpu = <&cpu0>;
72 };
73 core1 {
74 cpu = <&cpu1>;
75 };
76 };
77
78 cluster1 {
79 core0 {
80 cpu = <&cpu2>;
81 };
82 };
83 };
84
85 cpu0: cpu@0 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a35";
88 reg = <0x000>;
89 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
90 <&topckgen CLK_TOP_F_MP0_PLL1>;
91 clock-names = "cpu", "intermediate";
92 proc-supply = <&cpus_fixed_vproc0>;
93 operating-points-v2 = <&cluster0_opp>;
94 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
95 };
96
97 cpu1: cpu@1 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a35";
100 reg = <0x001>;
101 enable-method = "psci";
102 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
104 clock-names = "cpu", "intermediate";
105 proc-supply = <&cpus_fixed_vproc0>;
106 operating-points-v2 = <&cluster0_opp>;
107 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
108 };
109
110 cpu2: cpu@200 {
111 device_type = "cpu";
112 compatible = "arm,cortex-a72";
113 reg = <0x200>;
114 enable-method = "psci";
115 clocks = <&mcucfg CLK_MCU_MP2_SEL>,
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
117 clock-names = "cpu", "intermediate";
118 proc-supply = <&cpus_fixed_vproc1>;
119 operating-points-v2 = <&cluster1_opp>;
120 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
121 };
122
123 idle-states {
124 entry-method = "psci";
125
126 CPU_SLEEP_0: cpu-sleep-0 {
127 compatible = "arm,idle-state";
128 local-timer-stop;
129 entry-latency-us = <100>;
130 exit-latency-us = <80>;
131 min-residency-us = <2000>;
132 arm,psci-suspend-param = <0x0010000>;
133 };
134
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
136 compatible = "arm,idle-state";
137 local-timer-stop;
138 entry-latency-us = <350>;
139 exit-latency-us = <80>;
140 min-residency-us = <3000>;
141 arm,psci-suspend-param = <0x1010000>;
142 };
143 };
144 };
145
146 psci {
147 compatible = "arm,psci-0.2";
148 method = "smc";
149 };
150
151 baud_clk: dummy26m {
152 compatible = "fixed-clock";
153 clock-frequency = <26000000>;
154 #clock-cells = <0>;
155 };
156
157 sys_clk: dummyclk {
158 compatible = "fixed-clock";
159 clock-frequency = <26000000>;
160 #clock-cells = <0>;
161 };
162
163 clk26m: oscillator-26m {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <26000000>;
167 clock-output-names = "clk26m";
168 };
169
170 clk32k: oscillator-32k {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <32768>;
174 clock-output-names = "clk32k";
175 };
176
177 clkfpc: oscillator-50m {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <50000000>;
181 clock-output-names = "clkfpc";
182 };
183
184 clkaud_ext_i_0: oscillator-aud0 {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <6500000>;
188 clock-output-names = "clkaud_ext_i_0";
189 };
190
191 clkaud_ext_i_1: oscillator-aud1 {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <196608000>;
195 clock-output-names = "clkaud_ext_i_1";
196 };
197
198 clkaud_ext_i_2: oscillator-aud2 {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <180633600>;
202 clock-output-names = "clkaud_ext_i_2";
203 };
204
205 clki2si0_mck_i: oscillator-i2s0 {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <30000000>;
209 clock-output-names = "clki2si0_mck_i";
210 };
211
212 clki2si1_mck_i: oscillator-i2s1 {
213 compatible = "fixed-clock";
214 #clock-cells = <0>;
215 clock-frequency = <30000000>;
216 clock-output-names = "clki2si1_mck_i";
217 };
218
219 clki2si2_mck_i: oscillator-i2s2 {
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <30000000>;
223 clock-output-names = "clki2si2_mck_i";
224 };
225
226 clktdmin_mclk_i: oscillator-mclk {
227 compatible = "fixed-clock";
228 #clock-cells = <0>;
229 clock-frequency = <30000000>;
230 clock-output-names = "clktdmin_mclk_i";
231 };
232
233 timer {
234 compatible = "arm,armv8-timer";
235 interrupt-parent = <&gic>;
236 interrupts = <GIC_PPI 13
237 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
238 <GIC_PPI 14
239 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
240 <GIC_PPI 11
241 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
242 <GIC_PPI 10
243 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
244 };
245
246 topckgen: syscon@10000000 {
247 compatible = "mediatek,mt2712-topckgen", "syscon";
248 reg = <0 0x10000000 0 0x1000>;
249 #clock-cells = <1>;
250 };
251
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]252 infracfg: clock-controller@10001000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]253 compatible = "mediatek,mt2712-infracfg", "syscon";
254 reg = <0 0x10001000 0 0x1000>;
255 #clock-cells = <1>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]256 #reset-cells = <1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]257 };
258
259 pericfg: syscon@10003000 {
260 compatible = "mediatek,mt2712-pericfg", "syscon";
261 reg = <0 0x10003000 0 0x1000>;
262 #clock-cells = <1>;
263 };
264
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]265 syscfg_pctl_a: syscon@10005000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]266 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
267 reg = <0 0x10005000 0 0x1000>;
268 };
269
270 pio: pinctrl@1000b000 {
271 compatible = "mediatek,mt2712-pinctrl";
272 reg = <0 0x1000b000 0 0x1000>;
273 mediatek,pctl-regmap = <&syscfg_pctl_a>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
278 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
279 };
280
281 scpsys: power-controller@10006000 {
282 compatible = "mediatek,mt2712-scpsys", "syscon";
283 #power-domain-cells = <1>;
284 reg = <0 0x10006000 0 0x1000>;
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
290 <&topckgen CLK_TOP_VDEC_SEL>;
291 clock-names = "mm", "mfg", "venc",
292 "jpgdec", "audio", "vdec";
293 infracfg = <&infracfg>;
294 };
295
296 uart5: serial@1000f000 {
297 compatible = "mediatek,mt2712-uart",
298 "mediatek,mt6577-uart";
299 reg = <0 0x1000f000 0 0x400>;
300 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
301 clocks = <&baud_clk>, <&sys_clk>;
302 clock-names = "baud", "bus";
303 dmas = <&apdma 10
304 &apdma 11>;
305 dma-names = "tx", "rx";
306 status = "disabled";
307 };
308
309 rtc: rtc@10011000 {
310 compatible = "mediatek,mt2712-rtc";
311 reg = <0 0x10011000 0 0x1000>;
312 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
313 };
314
315 spis1: spi@10013000 {
316 compatible = "mediatek,mt2712-spi-slave";
317 reg = <0 0x10013000 0 0x100>;
318 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
319 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
320 clock-names = "spi";
321 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
323 status = "disabled";
324 };
325
326 iommu0: iommu@10205000 {
327 compatible = "mediatek,mt2712-m4u";
328 reg = <0 0x10205000 0 0x1000>;
329 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
330 clocks = <&infracfg CLK_INFRA_M4U>;
331 clock-names = "bclk";
332 mediatek,infracfg = <&infracfg>;
333 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
334 <&larb3>, <&larb6>;
335 #iommu-cells = <1>;
336 };
337
338 apmixedsys: syscon@10209000 {
339 compatible = "mediatek,mt2712-apmixedsys", "syscon";
340 reg = <0 0x10209000 0 0x1000>;
341 #clock-cells = <1>;
342 };
343
344 iommu1: iommu@1020a000 {
345 compatible = "mediatek,mt2712-m4u";
346 reg = <0 0x1020a000 0 0x1000>;
347 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
348 clocks = <&infracfg CLK_INFRA_M4U>;
349 clock-names = "bclk";
350 mediatek,infracfg = <&infracfg>;
351 mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
352 #iommu-cells = <1>;
353 };
354
355 mcucfg: syscon@10220000 {
356 compatible = "mediatek,mt2712-mcucfg", "syscon";
357 reg = <0 0x10220000 0 0x1000>;
358 #clock-cells = <1>;
359 };
360
361 sysirq: interrupt-controller@10220a80 {
362 compatible = "mediatek,mt2712-sysirq",
363 "mediatek,mt6577-sysirq";
364 interrupt-controller;
365 #interrupt-cells = <3>;
366 interrupt-parent = <&gic>;
367 reg = <0 0x10220a80 0 0x40>;
368 };
369
370 gic: interrupt-controller@10510000 {
371 compatible = "arm,gic-400";
372 #interrupt-cells = <3>;
373 interrupt-parent = <&gic>;
374 interrupt-controller;
375 reg = <0 0x10510000 0 0x10000>,
376 <0 0x10520000 0 0x20000>,
377 <0 0x10540000 0 0x20000>,
378 <0 0x10560000 0 0x20000>;
379 interrupts = <GIC_PPI 9
380 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
381 };
382
383 apdma: dma-controller@11000400 {
384 compatible = "mediatek,mt2712-uart-dma",
385 "mediatek,mt6577-uart-dma";
386 reg = <0 0x11000400 0 0x80>,
387 <0 0x11000480 0 0x80>,
388 <0 0x11000500 0 0x80>,
389 <0 0x11000580 0 0x80>,
390 <0 0x11000600 0 0x80>,
391 <0 0x11000680 0 0x80>,
392 <0 0x11000700 0 0x80>,
393 <0 0x11000780 0 0x80>,
394 <0 0x11000800 0 0x80>,
395 <0 0x11000880 0 0x80>,
396 <0 0x11000900 0 0x80>,
397 <0 0x11000980 0 0x80>;
398 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
399 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
400 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
401 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
402 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
403 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
404 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
405 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
406 <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
407 <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
408 <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
409 <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
410 dma-requests = <12>;
411 clocks = <&pericfg CLK_PERI_AP_DMA>;
412 clock-names = "apdma";
413 #dma-cells = <1>;
414 };
415
416 auxadc: adc@11001000 {
417 compatible = "mediatek,mt2712-auxadc";
418 reg = <0 0x11001000 0 0x1000>;
419 clocks = <&pericfg CLK_PERI_AUXADC>;
420 clock-names = "main";
421 #io-channel-cells = <1>;
422 status = "disabled";
423 };
424
425 uart0: serial@11002000 {
426 compatible = "mediatek,mt2712-uart",
427 "mediatek,mt6577-uart";
428 reg = <0 0x11002000 0 0x400>;
429 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
430 clocks = <&baud_clk>, <&sys_clk>;
431 clock-names = "baud", "bus";
432 dmas = <&apdma 0
433 &apdma 1>;
434 dma-names = "tx", "rx";
435 status = "disabled";
436 };
437
438 uart1: serial@11003000 {
439 compatible = "mediatek,mt2712-uart",
440 "mediatek,mt6577-uart";
441 reg = <0 0x11003000 0 0x400>;
442 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
443 clocks = <&baud_clk>, <&sys_clk>;
444 clock-names = "baud", "bus";
445 dmas = <&apdma 2
446 &apdma 3>;
447 dma-names = "tx", "rx";
448 status = "disabled";
449 };
450
451 uart2: serial@11004000 {
452 compatible = "mediatek,mt2712-uart",
453 "mediatek,mt6577-uart";
454 reg = <0 0x11004000 0 0x400>;
455 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
456 clocks = <&baud_clk>, <&sys_clk>;
457 clock-names = "baud", "bus";
458 dmas = <&apdma 4
459 &apdma 5>;
460 dma-names = "tx", "rx";
461 status = "disabled";
462 };
463
464 uart3: serial@11005000 {
465 compatible = "mediatek,mt2712-uart",
466 "mediatek,mt6577-uart";
467 reg = <0 0x11005000 0 0x400>;
468 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
469 clocks = <&baud_clk>, <&sys_clk>;
470 clock-names = "baud", "bus";
471 dmas = <&apdma 6
472 &apdma 7>;
473 dma-names = "tx", "rx";
474 status = "disabled";
475 };
476
477 pwm: pwm@11006000 {
478 compatible = "mediatek,mt2712-pwm";
479 reg = <0 0x11006000 0 0x1000>;
480 #pwm-cells = <2>;
481 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
482 clocks = <&topckgen CLK_TOP_PWM_SEL>,
483 <&pericfg CLK_PERI_PWM>,
484 <&pericfg CLK_PERI_PWM0>,
485 <&pericfg CLK_PERI_PWM1>,
486 <&pericfg CLK_PERI_PWM2>,
487 <&pericfg CLK_PERI_PWM3>,
488 <&pericfg CLK_PERI_PWM4>,
489 <&pericfg CLK_PERI_PWM5>,
490 <&pericfg CLK_PERI_PWM6>,
491 <&pericfg CLK_PERI_PWM7>;
492 clock-names = "top",
493 "main",
494 "pwm1",
495 "pwm2",
496 "pwm3",
497 "pwm4",
498 "pwm5",
499 "pwm6",
500 "pwm7",
501 "pwm8";
502 status = "disabled";
503 };
504
505 i2c0: i2c@11007000 {
506 compatible = "mediatek,mt2712-i2c";
507 reg = <0 0x11007000 0 0x90>,
508 <0 0x11000180 0 0x80>;
509 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
510 clock-div = <4>;
511 clocks = <&pericfg CLK_PERI_I2C0>,
512 <&pericfg CLK_PERI_AP_DMA>;
513 clock-names = "main",
514 "dma";
515 #address-cells = <1>;
516 #size-cells = <0>;
517 status = "disabled";
518 };
519
520 i2c1: i2c@11008000 {
521 compatible = "mediatek,mt2712-i2c";
522 reg = <0 0x11008000 0 0x90>,
523 <0 0x11000200 0 0x80>;
524 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
525 clock-div = <4>;
526 clocks = <&pericfg CLK_PERI_I2C1>,
527 <&pericfg CLK_PERI_AP_DMA>;
528 clock-names = "main",
529 "dma";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 status = "disabled";
533 };
534
535 i2c2: i2c@11009000 {
536 compatible = "mediatek,mt2712-i2c";
537 reg = <0 0x11009000 0 0x90>,
538 <0 0x11000280 0 0x80>;
539 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
540 clock-div = <4>;
541 clocks = <&pericfg CLK_PERI_I2C2>,
542 <&pericfg CLK_PERI_AP_DMA>;
543 clock-names = "main",
544 "dma";
545 #address-cells = <1>;
546 #size-cells = <0>;
547 status = "disabled";
548 };
549
550 spi0: spi@1100a000 {
551 compatible = "mediatek,mt2712-spi";
552 #address-cells = <1>;
553 #size-cells = <0>;
554 reg = <0 0x1100a000 0 0x100>;
555 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
556 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
557 <&topckgen CLK_TOP_SPI_SEL>,
558 <&pericfg CLK_PERI_SPI0>;
559 clock-names = "parent-clk", "sel-clk", "spi-clk";
560 status = "disabled";
561 };
562
563 nandc: nand-controller@1100e000 {
564 compatible = "mediatek,mt2712-nfc";
565 reg = <0 0x1100e000 0 0x1000>;
566 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
567 clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
568 clock-names = "nfi_clk", "pad_clk";
569 ecc-engine = <&bch>;
570 #address-cells = <1>;
571 #size-cells = <0>;
572 status = "disabled";
573 };
574
575 bch: ecc@1100f000 {
576 compatible = "mediatek,mt2712-ecc";
577 reg = <0 0x1100f000 0 0x1000>;
578 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
579 clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
580 clock-names = "nfiecc_clk";
581 status = "disabled";
582 };
583
584 i2c3: i2c@11010000 {
585 compatible = "mediatek,mt2712-i2c";
586 reg = <0 0x11010000 0 0x90>,
587 <0 0x11000300 0 0x80>;
588 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
589 clock-div = <4>;
590 clocks = <&pericfg CLK_PERI_I2C3>,
591 <&pericfg CLK_PERI_AP_DMA>;
592 clock-names = "main",
593 "dma";
594 #address-cells = <1>;
595 #size-cells = <0>;
596 status = "disabled";
597 };
598
599 i2c4: i2c@11011000 {
600 compatible = "mediatek,mt2712-i2c";
601 reg = <0 0x11011000 0 0x90>,
602 <0 0x11000380 0 0x80>;
603 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
604 clock-div = <4>;
605 clocks = <&pericfg CLK_PERI_I2C4>,
606 <&pericfg CLK_PERI_AP_DMA>;
607 clock-names = "main",
608 "dma";
609 #address-cells = <1>;
610 #size-cells = <0>;
611 status = "disabled";
612 };
613
614 i2c5: i2c@11013000 {
615 compatible = "mediatek,mt2712-i2c";
616 reg = <0 0x11013000 0 0x90>,
617 <0 0x11000100 0 0x80>;
618 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
619 clock-div = <4>;
620 clocks = <&pericfg CLK_PERI_I2C5>,
621 <&pericfg CLK_PERI_AP_DMA>;
622 clock-names = "main",
623 "dma";
624 #address-cells = <1>;
625 #size-cells = <0>;
626 status = "disabled";
627 };
628
629 spi2: spi@11015000 {
630 compatible = "mediatek,mt2712-spi";
631 #address-cells = <1>;
632 #size-cells = <0>;
633 reg = <0 0x11015000 0 0x100>;
634 interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>;
635 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
636 <&topckgen CLK_TOP_SPI_SEL>,
637 <&pericfg CLK_PERI_SPI2>;
638 clock-names = "parent-clk", "sel-clk", "spi-clk";
639 status = "disabled";
640 };
641
642 spi3: spi@11016000 {
643 compatible = "mediatek,mt2712-spi";
644 #address-cells = <1>;
645 #size-cells = <0>;
646 reg = <0 0x11016000 0 0x100>;
647 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
648 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
649 <&topckgen CLK_TOP_SPI_SEL>,
650 <&pericfg CLK_PERI_SPI3>;
651 clock-names = "parent-clk", "sel-clk", "spi-clk";
652 status = "disabled";
653 };
654
655 spi4: spi@10012000 {
656 compatible = "mediatek,mt2712-spi";
657 #address-cells = <1>;
658 #size-cells = <0>;
659 reg = <0 0x10012000 0 0x100>;
660 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>;
661 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
662 <&topckgen CLK_TOP_SPI_SEL>,
663 <&infracfg CLK_INFRA_AO_SPI0>;
664 clock-names = "parent-clk", "sel-clk", "spi-clk";
665 status = "disabled";
666 };
667
668 spi5: spi@11018000 {
669 compatible = "mediatek,mt2712-spi";
670 #address-cells = <1>;
671 #size-cells = <0>;
672 reg = <0 0x11018000 0 0x100>;
673 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>;
674 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
675 <&topckgen CLK_TOP_SPI_SEL>,
676 <&pericfg CLK_PERI_SPI5>;
677 clock-names = "parent-clk", "sel-clk", "spi-clk";
678 status = "disabled";
679 };
680
681 uart4: serial@11019000 {
682 compatible = "mediatek,mt2712-uart",
683 "mediatek,mt6577-uart";
684 reg = <0 0x11019000 0 0x400>;
685 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
686 clocks = <&baud_clk>, <&sys_clk>;
687 clock-names = "baud", "bus";
688 dmas = <&apdma 8
689 &apdma 9>;
690 dma-names = "tx", "rx";
691 status = "disabled";
692 };
693
694 stmmac_axi_setup: stmmac-axi-config {
695 snps,wr_osr_lmt = <0x7>;
696 snps,rd_osr_lmt = <0x7>;
697 snps,blen = <0 0 0 0 16 8 4>;
698 };
699
700 mtl_rx_setup: rx-queues-config {
701 snps,rx-queues-to-use = <1>;
702 snps,rx-sched-sp;
703 queue0 {
704 snps,dcb-algorithm;
705 snps,map-to-dma-channel = <0x0>;
706 snps,priority = <0x0>;
707 };
708 };
709
710 mtl_tx_setup: tx-queues-config {
711 snps,tx-queues-to-use = <3>;
712 snps,tx-sched-wrr;
713 queue0 {
714 snps,weight = <0x10>;
715 snps,dcb-algorithm;
716 snps,priority = <0x0>;
717 };
718 queue1 {
719 snps,weight = <0x11>;
720 snps,dcb-algorithm;
721 snps,priority = <0x1>;
722 };
723 queue2 {
724 snps,weight = <0x12>;
725 snps,dcb-algorithm;
726 snps,priority = <0x2>;
727 };
728 };
729
730 eth: ethernet@1101c000 {
731 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
732 reg = <0 0x1101c000 0 0x1300>;
733 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
734 interrupt-names = "macirq";
735 mac-address = [00 55 7b b5 7d f7];
736 clock-names = "axi",
737 "apb",
738 "mac_main",
739 "ptp_ref",
740 "rmii_internal";
741 clocks = <&pericfg CLK_PERI_GMAC>,
742 <&pericfg CLK_PERI_GMAC_PCLK>,
743 <&topckgen CLK_TOP_ETHER_125M_SEL>,
744 <&topckgen CLK_TOP_ETHER_50M_SEL>,
745 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
746 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
747 <&topckgen CLK_TOP_ETHER_50M_SEL>,
748 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
749 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
750 <&topckgen CLK_TOP_APLL1_D3>,
751 <&topckgen CLK_TOP_ETHERPLL_50M>;
752 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
753 mediatek,pericfg = <&pericfg>;
754 snps,axi-config = <&stmmac_axi_setup>;
755 snps,mtl-rx-config = <&mtl_rx_setup>;
756 snps,mtl-tx-config = <&mtl_tx_setup>;
757 snps,txpbl = <1>;
758 snps,rxpbl = <1>;
759 snps,clk-csr = <0>;
760 status = "disabled";
761 };
762
763 mmc0: mmc@11230000 {
764 compatible = "mediatek,mt2712-mmc";
765 reg = <0 0x11230000 0 0x1000>;
766 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
767 clocks = <&pericfg CLK_PERI_MSDC30_0>,
768 <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
769 <&pericfg CLK_PERI_MSDC50_0_EN>,
770 <&pericfg CLK_PERI_MSDC30_0_QTR_EN>;
771 clock-names = "source", "hclk", "source_cg", "bus_clk";
772 status = "disabled";
773 };
774
775 mmc1: mmc@11240000 {
776 compatible = "mediatek,mt2712-mmc";
777 reg = <0 0x11240000 0 0x1000>;
778 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
779 clocks = <&pericfg CLK_PERI_MSDC30_1>,
780 <&topckgen CLK_TOP_AXI_SEL>,
781 <&pericfg CLK_PERI_MSDC30_1_EN>;
782 clock-names = "source", "hclk", "source_cg";
783 status = "disabled";
784 };
785
786 mmc2: mmc@11250000 {
787 compatible = "mediatek,mt2712-mmc";
788 reg = <0 0x11250000 0 0x1000>;
789 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
790 clocks = <&pericfg CLK_PERI_MSDC30_2>,
791 <&topckgen CLK_TOP_AXI_SEL>,
792 <&pericfg CLK_PERI_MSDC30_2_EN>;
793 clock-names = "source", "hclk", "source_cg";
794 status = "disabled";
795 };
796
797 ssusb: usb@11271000 {
798 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
799 reg = <0 0x11271000 0 0x3000>,
800 <0 0x11280700 0 0x0100>;
801 reg-names = "mac", "ippc";
802 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
803 phys = <&u2port0 PHY_TYPE_USB2>,
804 <&u2port1 PHY_TYPE_USB2>;
805 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
806 clocks = <&topckgen CLK_TOP_USB30_SEL>;
807 clock-names = "sys_ck";
808 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
809 #address-cells = <2>;
810 #size-cells = <2>;
811 ranges;
812 status = "disabled";
813
814 usb_host0: usb@11270000 {
815 compatible = "mediatek,mt2712-xhci",
816 "mediatek,mtk-xhci";
817 reg = <0 0x11270000 0 0x1000>;
818 reg-names = "mac";
819 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>;
820 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
821 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
822 clock-names = "sys_ck", "ref_ck";
823 status = "disabled";
824 };
825 };
826
827 u3phy0: t-phy@11290000 {
828 compatible = "mediatek,mt2712-tphy",
829 "mediatek,generic-tphy-v2";
830 #address-cells = <1>;
831 #size-cells = <1>;
832 ranges = <0 0 0x11290000 0x9000>;
833 status = "okay";
834
835 u2port0: usb-phy@0 {
836 reg = <0x0 0x700>;
837 clocks = <&clk26m>;
838 clock-names = "ref";
839 #phy-cells = <1>;
840 status = "okay";
841 };
842
843 u2port1: usb-phy@8000 {
844 reg = <0x8000 0x700>;
845 clocks = <&clk26m>;
846 clock-names = "ref";
847 #phy-cells = <1>;
848 status = "okay";
849 };
850
851 u3port0: usb-phy@8700 {
852 reg = <0x8700 0x900>;
853 clocks = <&clk26m>;
854 clock-names = "ref";
855 #phy-cells = <1>;
856 status = "okay";
857 };
858 };
859
860 ssusb1: usb@112c1000 {
861 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
862 reg = <0 0x112c1000 0 0x3000>,
863 <0 0x112d0700 0 0x0100>;
864 reg-names = "mac", "ippc";
865 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>;
866 phys = <&u2port2 PHY_TYPE_USB2>,
867 <&u2port3 PHY_TYPE_USB2>,
868 <&u3port1 PHY_TYPE_USB3>;
869 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
870 clocks = <&topckgen CLK_TOP_USB30_SEL>;
871 clock-names = "sys_ck";
872 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
873 #address-cells = <2>;
874 #size-cells = <2>;
875 ranges;
876 status = "disabled";
877
878 usb_host1: usb@112c0000 {
879 compatible = "mediatek,mt2712-xhci",
880 "mediatek,mtk-xhci";
881 reg = <0 0x112c0000 0 0x1000>;
882 reg-names = "mac";
883 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
884 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
885 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
886 clock-names = "sys_ck", "ref_ck";
887 status = "disabled";
888 };
889 };
890
891 u3phy1: t-phy@112e0000 {
892 compatible = "mediatek,mt2712-tphy",
893 "mediatek,generic-tphy-v2";
894 #address-cells = <1>;
895 #size-cells = <1>;
896 ranges = <0 0 0x112e0000 0x9000>;
897 status = "okay";
898
899 u2port2: usb-phy@0 {
900 reg = <0x0 0x700>;
901 clocks = <&clk26m>;
902 clock-names = "ref";
903 #phy-cells = <1>;
904 status = "okay";
905 };
906
907 u2port3: usb-phy@8000 {
908 reg = <0x8000 0x700>;
909 clocks = <&clk26m>;
910 clock-names = "ref";
911 #phy-cells = <1>;
912 status = "okay";
913 };
914
915 u3port1: usb-phy@8700 {
916 reg = <0x8700 0x900>;
917 clocks = <&clk26m>;
918 clock-names = "ref";
919 #phy-cells = <1>;
920 status = "okay";
921 };
922 };
923
924 pcie1: pcie@112ff000 {
925 compatible = "mediatek,mt2712-pcie";
926 device_type = "pci";
927 reg = <0 0x112ff000 0 0x1000>;
928 reg-names = "port1";
929 linux,pci-domain = <1>;
930 #address-cells = <3>;
931 #size-cells = <2>;
932 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
933 interrupt-names = "pcie_irq";
934 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
935 <&pericfg CLK_PERI_PCIE1>;
936 clock-names = "sys_ck1", "ahb_ck1";
937 phys = <&u3port1 PHY_TYPE_PCIE>;
938 phy-names = "pcie-phy1";
939 bus-range = <0x00 0xff>;
940 ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
941 status = "disabled";
942
943 #interrupt-cells = <1>;
944 interrupt-map-mask = <0 0 0 7>;
945 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
946 <0 0 0 2 &pcie_intc1 1>,
947 <0 0 0 3 &pcie_intc1 2>,
948 <0 0 0 4 &pcie_intc1 3>;
949 pcie_intc1: interrupt-controller {
950 interrupt-controller;
951 #address-cells = <0>;
952 #interrupt-cells = <1>;
953 };
954 };
955
956 pcie0: pcie@11700000 {
957 compatible = "mediatek,mt2712-pcie";
958 device_type = "pci";
959 reg = <0 0x11700000 0 0x1000>;
960 reg-names = "port0";
961 linux,pci-domain = <0>;
962 #address-cells = <3>;
963 #size-cells = <2>;
964 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-names = "pcie_irq";
966 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
967 <&pericfg CLK_PERI_PCIE0>;
968 clock-names = "sys_ck0", "ahb_ck0";
969 phys = <&u3port0 PHY_TYPE_PCIE>;
970 phy-names = "pcie-phy0";
971 bus-range = <0x00 0xff>;
972 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
973 status = "disabled";
974
975 #interrupt-cells = <1>;
976 interrupt-map-mask = <0 0 0 7>;
977 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
978 <0 0 0 2 &pcie_intc0 1>,
979 <0 0 0 3 &pcie_intc0 2>,
980 <0 0 0 4 &pcie_intc0 3>;
981 pcie_intc0: interrupt-controller {
982 interrupt-controller;
983 #address-cells = <0>;
984 #interrupt-cells = <1>;
985 };
986 };
987
988 mfgcfg: syscon@13000000 {
989 compatible = "mediatek,mt2712-mfgcfg", "syscon";
990 reg = <0 0x13000000 0 0x1000>;
991 #clock-cells = <1>;
992 };
993
994 mmsys: syscon@14000000 {
995 compatible = "mediatek,mt2712-mmsys", "syscon";
996 reg = <0 0x14000000 0 0x1000>;
997 #clock-cells = <1>;
998 };
999
1000 larb0: larb@14021000 {
1001 compatible = "mediatek,mt2712-smi-larb";
1002 reg = <0 0x14021000 0 0x1000>;
1003 mediatek,smi = <&smi_common0>;
1004 mediatek,larb-id = <0>;
1005 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1006 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1007 <&mmsys CLK_MM_SMI_LARB0>;
1008 clock-names = "apb", "smi";
1009 };
1010
1011 smi_common0: smi@14022000 {
1012 compatible = "mediatek,mt2712-smi-common";
1013 reg = <0 0x14022000 0 0x1000>;
1014 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1015 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1016 <&mmsys CLK_MM_SMI_COMMON>;
1017 clock-names = "apb", "smi";
1018 };
1019
1020 larb4: larb@14027000 {
1021 compatible = "mediatek,mt2712-smi-larb";
1022 reg = <0 0x14027000 0 0x1000>;
1023 mediatek,smi = <&smi_common1>;
1024 mediatek,larb-id = <4>;
1025 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1026 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1027 <&mmsys CLK_MM_SMI_LARB4>;
1028 clock-names = "apb", "smi";
1029 };
1030
1031 larb5: larb@14030000 {
1032 compatible = "mediatek,mt2712-smi-larb";
1033 reg = <0 0x14030000 0 0x1000>;
1034 mediatek,smi = <&smi_common1>;
1035 mediatek,larb-id = <5>;
1036 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1037 clocks = <&mmsys CLK_MM_SMI_LARB5>,
1038 <&mmsys CLK_MM_SMI_LARB5>;
1039 clock-names = "apb", "smi";
1040 };
1041
1042 smi_common1: smi@14031000 {
1043 compatible = "mediatek,mt2712-smi-common";
1044 reg = <0 0x14031000 0 0x1000>;
1045 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1046 clocks = <&mmsys CLK_MM_SMI_COMMON1>,
1047 <&mmsys CLK_MM_SMI_COMMON1>;
1048 clock-names = "apb", "smi";
1049 };
1050
1051 larb7: larb@14032000 {
1052 compatible = "mediatek,mt2712-smi-larb";
1053 reg = <0 0x14032000 0 0x1000>;
1054 mediatek,smi = <&smi_common1>;
1055 mediatek,larb-id = <7>;
1056 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1057 clocks = <&mmsys CLK_MM_SMI_LARB7>,
1058 <&mmsys CLK_MM_SMI_LARB7>;
1059 clock-names = "apb", "smi";
1060 };
1061
1062 imgsys: syscon@15000000 {
1063 compatible = "mediatek,mt2712-imgsys", "syscon";
1064 reg = <0 0x15000000 0 0x1000>;
1065 #clock-cells = <1>;
1066 };
1067
1068 larb2: larb@15001000 {
1069 compatible = "mediatek,mt2712-smi-larb";
1070 reg = <0 0x15001000 0 0x1000>;
1071 mediatek,smi = <&smi_common0>;
1072 mediatek,larb-id = <2>;
1073 power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
1074 clocks = <&imgsys CLK_IMG_SMI_LARB2>,
1075 <&imgsys CLK_IMG_SMI_LARB2>;
1076 clock-names = "apb", "smi";
1077 };
1078
1079 bdpsys: syscon@15010000 {
1080 compatible = "mediatek,mt2712-bdpsys", "syscon";
1081 reg = <0 0x15010000 0 0x1000>;
1082 #clock-cells = <1>;
1083 };
1084
1085 vdecsys: syscon@16000000 {
1086 compatible = "mediatek,mt2712-vdecsys", "syscon";
1087 reg = <0 0x16000000 0 0x1000>;
1088 #clock-cells = <1>;
1089 };
1090
1091 larb1: larb@16010000 {
1092 compatible = "mediatek,mt2712-smi-larb";
1093 reg = <0 0x16010000 0 0x1000>;
1094 mediatek,smi = <&smi_common0>;
1095 mediatek,larb-id = <1>;
1096 power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
1097 clocks = <&vdecsys CLK_VDEC_CKEN>,
1098 <&vdecsys CLK_VDEC_LARB1_CKEN>;
1099 clock-names = "apb", "smi";
1100 };
1101
1102 vencsys: syscon@18000000 {
1103 compatible = "mediatek,mt2712-vencsys", "syscon";
1104 reg = <0 0x18000000 0 0x1000>;
1105 #clock-cells = <1>;
1106 };
1107
1108 larb3: larb@18001000 {
1109 compatible = "mediatek,mt2712-smi-larb";
1110 reg = <0 0x18001000 0 0x1000>;
1111 mediatek,smi = <&smi_common0>;
1112 mediatek,larb-id = <3>;
1113 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1114 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1115 <&vencsys CLK_VENC_VENC>;
1116 clock-names = "apb", "smi";
1117 };
1118
1119 larb6: larb@18002000 {
1120 compatible = "mediatek,mt2712-smi-larb";
1121 reg = <0 0x18002000 0 0x1000>;
1122 mediatek,smi = <&smi_common0>;
1123 mediatek,larb-id = <6>;
1124 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1125 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1126 <&vencsys CLK_VENC_VENC>;
1127 clock-names = "apb", "smi";
1128 };
1129
1130 jpgdecsys: syscon@19000000 {
1131 compatible = "mediatek,mt2712-jpgdecsys", "syscon";
1132 reg = <0 0x19000000 0 0x1000>;
1133 #clock-cells = <1>;
1134 };
1135};
1136