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git01.mediatek.com / filogic / uboot / 0d063f338ac660a007986af438eb8c64062ad88a / . / dts / upstream / src / arm / microchip / sama5d4.dtsi
blob: 58ceed997889bfa4e73e365e6d2bcb35e2e2f4fe [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
4 *
5 * Copyright (C) 2014 Atmel,
6 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
7 */
8
9#include <dt-bindings/clock/at91.h>
10#include <dt-bindings/dma/at91.h>
11#include <dt-bindings/mfd/at91-usart.h>
12#include <dt-bindings/pinctrl/at91.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/gpio/gpio.h>
15
16/ {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 model = "Atmel SAMA5D4 family SoC";
20 compatible = "atmel,sama5d4";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &usart3;
25 serial1 = &usart4;
26 serial2 = &usart2;
27 serial3 = &usart0;
28 serial4 = &usart1;
29 serial5 = &uart0;
30 serial6 = &uart1;
31 gpio0 = &pioA;
32 gpio1 = &pioB;
33 gpio2 = &pioC;
34 gpio3 = &pioD;
35 gpio4 = &pioE;
36 pwm0 = &pwm0;
37 ssc0 = &ssc0;
38 ssc1 = &ssc1;
39 tcb0 = &tcb0;
40 tcb1 = &tcb1;
41 i2c0 = &i2c0;
42 i2c1 = &i2c1;
43 i2c2 = &i2c2;
44 };
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a5";
52 reg = <0>;
53 next-level-cache = <&L2>;
54 };
55 };
56
57 memory@20000000 {
58 device_type = "memory";
59 reg = <0x20000000 0x20000000>;
60 };
61
62 clocks {
63 slow_xtal: slow_xtal {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
68
69 main_xtal: main_xtal {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <0>;
73 };
74
75 adc_op_clk: adc_op_clk {
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <1000000>;
79 };
80 };
81
82 ns_sram: sram@210000 {
83 compatible = "mmio-sram";
84 reg = <0x00210000 0x10000>;
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges = <0 0x00210000 0x10000>;
88 };
89
90 ahb {
91 compatible = "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
95
96 nfc_sram: sram@100000 {
97 compatible = "mmio-sram";
98 no-memory-wc;
99 reg = <0x100000 0x2400>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0 0x100000 0x2400>;
103 };
104
105 vdec0: vdec@300000 {
106 compatible = "microchip,sama5d4-vdec";
107 reg = <0x00300000 0x100000>;
108 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
109 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
110 };
111
112 usb0: gadget@400000 {
113 compatible = "atmel,sama5d3-udc";
114 reg = <0x00400000 0x100000
115 0xfc02c000 0x4000>;
116 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
117 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
118 clock-names = "pclk", "hclk";
119 status = "disabled";
120 };
121
122 usb1: ohci@500000 {
123 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
124 reg = <0x00500000 0x100000>;
125 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
126 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>;
127 clock-names = "ohci_clk", "hclk", "uhpck";
128 status = "disabled";
129 };
130
131 usb2: ehci@600000 {
132 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
133 reg = <0x00600000 0x100000>;
134 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
135 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>;
136 clock-names = "usb_clk", "ehci_clk";
137 status = "disabled";
138 };
139
140 L2: cache-controller@a00000 {
141 compatible = "arm,pl310-cache";
142 reg = <0x00a00000 0x1000>;
143 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
144 cache-unified;
145 cache-level = <2>;
146 };
147
148 ebi: ebi@10000000 {
149 compatible = "atmel,sama5d3-ebi";
150 #address-cells = <2>;
151 #size-cells = <1>;
152 atmel,smc = <&hsmc>;
153 reg = <0x10000000 0x10000000
154 0x60000000 0x28000000>;
155 ranges = <0x0 0x0 0x10000000 0x10000000
156 0x1 0x0 0x60000000 0x10000000
157 0x2 0x0 0x70000000 0x10000000
158 0x3 0x0 0x80000000 0x8000000>;
159 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
160 status = "disabled";
161
162 nand_controller: nand-controller {
163 compatible = "atmel,sama5d3-nand-controller";
164 atmel,nfc-sram = <&nfc_sram>;
165 atmel,nfc-io = <&nfc_io>;
166 ecc-engine = <&pmecc>;
167 #address-cells = <2>;
168 #size-cells = <1>;
169 ranges;
170 status = "disabled";
171 };
172 };
173
174 nfc_io: nfc-io@90000000 {
175 compatible = "atmel,sama5d3-nfc-io", "syscon";
176 reg = <0x90000000 0x8000000>;
177 };
178
179 apb {
180 compatible = "simple-bus";
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges;
184
185 hlcdc: hlcdc@f0000000 {
186 compatible = "atmel,sama5d4-hlcdc";
187 reg = <0xf0000000 0x4000>;
188 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
189 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
190 clock-names = "periph_clk","sys_clk", "slow_clk";
191 status = "disabled";
192
193 hlcdc-display-controller {
194 compatible = "atmel,hlcdc-display-controller";
195 #address-cells = <1>;
196 #size-cells = <0>;
197
198 port@0 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 reg = <0>;
202 };
203 };
204
205 hlcdc_pwm: hlcdc-pwm {
206 compatible = "atmel,hlcdc-pwm";
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_lcd_pwm>;
209 #pwm-cells = <3>;
210 };
211 };
212
213 dma1: dma-controller@f0004000 {
214 compatible = "atmel,sama5d4-dma";
215 reg = <0xf0004000 0x200>;
216 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
217 #dma-cells = <1>;
218 clocks = <&pmc PMC_TYPE_PERIPHERAL 50>;
219 clock-names = "dma_clk";
220 };
221
222 isi: isi@f0008000 {
223 compatible = "atmel,at91sam9g45-isi";
224 reg = <0xf0008000 0x4000>;
225 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_isi_data_0_7>;
228 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
229 clock-names = "isi_clk";
230 status = "disabled";
231 port {
232 #address-cells = <1>;
233 #size-cells = <0>;
234 };
235 };
236
237 ramc0: ramc@f0010000 {
238 compatible = "atmel,sama5d3-ddramc";
239 reg = <0xf0010000 0x200>;
240 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>;
241 clock-names = "ddrck", "mpddr";
242 };
243
244 dma0: dma-controller@f0014000 {
245 compatible = "atmel,sama5d4-dma";
246 reg = <0xf0014000 0x200>;
247 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
248 #dma-cells = <1>;
249 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
250 clock-names = "dma_clk";
251 };
252
253 pmc: clock-controller@f0018000 {
254 compatible = "atmel,sama5d4-pmc", "syscon";
255 reg = <0xf0018000 0x120>;
256 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
257 #clock-cells = <2>;
258 clocks = <&clk32k>, <&main_xtal>;
259 clock-names = "slow_clk", "main_xtal";
260 };
261
262 mmc0: mmc@f8000000 {
263 compatible = "atmel,hsmci";
264 reg = <0xf8000000 0x600>;
265 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
266 dmas = <&dma1
267 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
268 | AT91_XDMAC_DT_PERID(0))>;
269 dma-names = "rxtx";
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
272 status = "disabled";
273 #address-cells = <1>;
274 #size-cells = <0>;
275 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
276 clock-names = "mci_clk";
277 };
278
279 uart0: serial@f8004000 {
280 compatible = "atmel,at91sam9260-usart";
281 reg = <0xf8004000 0x100>;
282 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
283 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
284 dmas = <&dma0
285 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
286 | AT91_XDMAC_DT_PERID(22))>,
287 <&dma0
288 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
289 | AT91_XDMAC_DT_PERID(23))>;
290 dma-names = "tx", "rx";
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_uart0>;
293 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
294 clock-names = "usart";
295 status = "disabled";
296 };
297
298 ssc0: ssc@f8008000 {
299 compatible = "atmel,at91sam9g45-ssc";
300 reg = <0xf8008000 0x4000>;
301 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
304 dmas = <&dma1
305 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
306 | AT91_XDMAC_DT_PERID(26))>,
307 <&dma1
308 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
309 | AT91_XDMAC_DT_PERID(27))>;
310 dma-names = "tx", "rx";
311 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
312 clock-names = "pclk";
313 status = "disabled";
314 };
315
316 pwm0: pwm@f800c000 {
317 compatible = "atmel,sama5d3-pwm";
318 reg = <0xf800c000 0x300>;
319 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
320 #pwm-cells = <3>;
321 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
322 status = "disabled";
323 };
324
325 spi0: spi@f8010000 {
326 #address-cells = <1>;
327 #size-cells = <0>;
328 compatible = "atmel,at91rm9200-spi";
329 reg = <0xf8010000 0x100>;
330 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
331 dmas = <&dma1
332 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
333 | AT91_XDMAC_DT_PERID(10))>,
334 <&dma1
335 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
336 | AT91_XDMAC_DT_PERID(11))>;
337 dma-names = "tx", "rx";
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_spi0>;
340 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
341 clock-names = "spi_clk";
342 status = "disabled";
343 };
344
345 i2c0: i2c@f8014000 {
346 compatible = "atmel,sama5d4-i2c";
347 reg = <0xf8014000 0x4000>;
348 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
349 dmas = <&dma1
350 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
351 | AT91_XDMAC_DT_PERID(2))>,
352 <&dma1
353 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
354 | AT91_XDMAC_DT_PERID(3))>;
355 dma-names = "tx", "rx";
356 pinctrl-names = "default", "gpio";
357 pinctrl-0 = <&pinctrl_i2c0>;
358 pinctrl-1 = <&pinctrl_i2c0_gpio>;
359 sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
360 scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
364 status = "disabled";
365 };
366
367 i2c1: i2c@f8018000 {
368 compatible = "atmel,sama5d4-i2c";
369 reg = <0xf8018000 0x4000>;
370 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
371 dmas = <&dma0
372 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
373 | AT91_XDMAC_DT_PERID(4))>,
374 <&dma0
375 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
376 | AT91_XDMAC_DT_PERID(5))>;
377 dma-names = "tx", "rx";
378 pinctrl-names = "default", "gpio";
379 pinctrl-0 = <&pinctrl_i2c1>;
380 pinctrl-1 = <&pinctrl_i2c1_gpio>;
381 sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
382 scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
386 status = "disabled";
387 };
388
389 tcb0: timer@f801c000 {
390 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
391 #address-cells = <1>;
392 #size-cells = <0>;
393 reg = <0xf801c000 0x100>;
394 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
395 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>;
396 clock-names = "t0_clk", "slow_clk";
397 };
398
399 macb0: ethernet@f8020000 {
400 compatible = "atmel,sama5d4-gem";
401 reg = <0xf8020000 0x100>;
402 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_macb0_rmii>;
405 #address-cells = <1>;
406 #size-cells = <0>;
407 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>;
408 clock-names = "hclk", "pclk";
409 status = "disabled";
410 };
411
412 i2c2: i2c@f8024000 {
413 compatible = "atmel,sama5d4-i2c";
414 reg = <0xf8024000 0x4000>;
415 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
416 dmas = <&dma1
417 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
418 | AT91_XDMAC_DT_PERID(6))>,
419 <&dma1
420 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
421 | AT91_XDMAC_DT_PERID(7))>;
422 dma-names = "tx", "rx";
423 pinctrl-names = "default", "gpio";
424 pinctrl-0 = <&pinctrl_i2c2>;
425 pinctrl-1 = <&pinctrl_i2c2_gpio>;
426 sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>;
427 scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
428 #address-cells = <1>;
429 #size-cells = <0>;
430 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
431 status = "disabled";
432 };
433
434 sfr: sfr@f8028000 {
435 compatible = "atmel,sama5d4-sfr", "syscon";
436 reg = <0xf8028000 0x60>;
437 };
438
439 usart0: serial@f802c000 {
440 compatible = "atmel,at91sam9260-usart";
441 reg = <0xf802c000 0x100>;
442 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
443 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
444 dmas = <&dma0
445 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
446 | AT91_XDMAC_DT_PERID(36))>,
447 <&dma0
448 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
449 | AT91_XDMAC_DT_PERID(37))>;
450 dma-names = "tx", "rx";
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
453 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
454 clock-names = "usart";
455 status = "disabled";
456 };
457
458 usart1: serial@f8030000 {
459 compatible = "atmel,at91sam9260-usart";
460 reg = <0xf8030000 0x100>;
461 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
462 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
463 dmas = <&dma0
464 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
465 | AT91_XDMAC_DT_PERID(38))>,
466 <&dma0
467 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
468 | AT91_XDMAC_DT_PERID(39))>;
469 dma-names = "tx", "rx";
470 pinctrl-names = "default";
471 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
472 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
473 clock-names = "usart";
474 status = "disabled";
475 };
476
477 mmc1: mmc@fc000000 {
478 compatible = "atmel,hsmci";
479 reg = <0xfc000000 0x600>;
480 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
481 dmas = <&dma1
482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
483 | AT91_XDMAC_DT_PERID(1))>;
484 dma-names = "rxtx";
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
487 status = "disabled";
488 #address-cells = <1>;
489 #size-cells = <0>;
490 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
491 clock-names = "mci_clk";
492 };
493
494 uart1: serial@fc004000 {
495 compatible = "atmel,at91sam9260-usart";
496 reg = <0xfc004000 0x100>;
497 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
498 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
499 dmas = <&dma0
500 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
501 | AT91_XDMAC_DT_PERID(24))>,
502 <&dma0
503 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
504 | AT91_XDMAC_DT_PERID(25))>;
505 dma-names = "tx", "rx";
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_uart1>;
508 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
509 clock-names = "usart";
510 status = "disabled";
511 };
512
513 usart2: serial@fc008000 {
514 compatible = "atmel,at91sam9260-usart";
515 reg = <0xfc008000 0x100>;
516 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
517 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
518 dmas = <&dma1
519 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
520 | AT91_XDMAC_DT_PERID(16))>,
521 <&dma1
522 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
523 | AT91_XDMAC_DT_PERID(17))>;
524 dma-names = "tx", "rx";
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
527 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
528 clock-names = "usart";
529 status = "disabled";
530 };
531
532 usart3: serial@fc00c000 {
533 compatible = "atmel,at91sam9260-usart";
534 reg = <0xfc00c000 0x100>;
535 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
536 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
537 dmas = <&dma1
538 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
539 | AT91_XDMAC_DT_PERID(18))>,
540 <&dma1
541 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
542 | AT91_XDMAC_DT_PERID(19))>;
543 dma-names = "tx", "rx";
544 pinctrl-names = "default";
545 pinctrl-0 = <&pinctrl_usart3>;
546 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
547 clock-names = "usart";
548 status = "disabled";
549 };
550
551 usart4: serial@fc010000 {
552 compatible = "atmel,at91sam9260-usart";
553 reg = <0xfc010000 0x100>;
554 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
555 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
556 dmas = <&dma1
557 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
558 | AT91_XDMAC_DT_PERID(20))>,
559 <&dma1
560 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
561 | AT91_XDMAC_DT_PERID(21))>;
562 dma-names = "tx", "rx";
563 pinctrl-names = "default";
564 pinctrl-0 = <&pinctrl_usart4>;
565 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
566 clock-names = "usart";
567 status = "disabled";
568 };
569
570 ssc1: ssc@fc014000 {
571 compatible = "atmel,at91sam9g45-ssc";
572 reg = <0xfc014000 0x4000>;
573 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
576 dmas = <&dma1
577 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
578 | AT91_XDMAC_DT_PERID(28))>,
579 <&dma1
580 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
581 | AT91_XDMAC_DT_PERID(29))>;
582 dma-names = "tx", "rx";
583 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
584 clock-names = "pclk";
585 status = "disabled";
586 };
587
588 spi1: spi@fc018000 {
589 #address-cells = <1>;
590 #size-cells = <0>;
591 compatible = "atmel,at91rm9200-spi";
592 reg = <0xfc018000 0x100>;
593 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
594 dmas = <&dma1
595 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
596 | AT91_XDMAC_DT_PERID(12))>,
597 <&dma1
598 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
599 | AT91_XDMAC_DT_PERID(13))>;
600 dma-names = "tx", "rx";
601 pinctrl-names = "default";
602 pinctrl-0 = <&pinctrl_spi1>;
603 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
604 clock-names = "spi_clk";
605 status = "disabled";
606 };
607
608 spi2: spi@fc01c000 {
609 #address-cells = <1>;
610 #size-cells = <0>;
611 compatible = "atmel,at91rm9200-spi";
612 reg = <0xfc01c000 0x100>;
613 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
614 dmas = <&dma0
615 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
616 | AT91_XDMAC_DT_PERID(14))>,
617 <&dma0
618 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
619 | AT91_XDMAC_DT_PERID(15))>;
620 dma-names = "tx", "rx";
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_spi2>;
623 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
624 clock-names = "spi_clk";
625 status = "disabled";
626 };
627
628 tcb1: timer@fc020000 {
629 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
630 #address-cells = <1>;
631 #size-cells = <0>;
632 reg = <0xfc020000 0x100>;
633 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
634 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>;
635 clock-names = "t0_clk", "slow_clk";
636 };
637
638 tcb2: timer@fc024000 {
639 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
640 #address-cells = <1>;
641 #size-cells = <0>;
642 reg = <0xfc024000 0x100>;
643 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
644 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>;
645 clock-names = "t0_clk", "slow_clk";
646 };
647
648 macb1: ethernet@fc028000 {
649 compatible = "atmel,sama5d4-gem";
650 reg = <0xfc028000 0x100>;
651 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&pinctrl_macb1_rmii>;
654 #address-cells = <1>;
655 #size-cells = <0>;
656 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>;
657 clock-names = "hclk", "pclk";
658 status = "disabled";
659 };
660
661 trng@fc030000 {
662 compatible = "atmel,at91sam9g45-trng";
663 reg = <0xfc030000 0x100>;
664 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
665 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
666 };
667
668 adc0: adc@fc034000 {
669 compatible = "atmel,at91sam9x5-adc";
670 reg = <0xfc034000 0x100>;
671 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
672 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>,
673 <&adc_op_clk>;
674 clock-names = "adc_clk", "adc_op_clk";
675 atmel,adc-channels-used = <0x01f>;
676 atmel,adc-startup-time = <40>;
677 atmel,adc-use-external-triggers;
678 atmel,adc-vref = <3000>;
679 atmel,adc-sample-hold-time = <11>;
680 atmel,adc-ts-pressure-threshold = <10000>;
681 status = "disabled";
682 };
683
684 aes: crypto@fc044000 {
685 compatible = "atmel,at91sam9g46-aes";
686 reg = <0xfc044000 0x100>;
687 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
688 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
689 | AT91_XDMAC_DT_PERID(41))>,
690 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
691 | AT91_XDMAC_DT_PERID(40))>;
692 dma-names = "tx", "rx";
693 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
694 clock-names = "aes_clk";
695 };
696
697 tdes: crypto@fc04c000 {
698 compatible = "atmel,at91sam9g46-tdes";
699 reg = <0xfc04c000 0x100>;
700 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
701 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
702 | AT91_XDMAC_DT_PERID(42))>,
703 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
704 | AT91_XDMAC_DT_PERID(43))>;
705 dma-names = "tx", "rx";
706 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
707 clock-names = "tdes_clk";
708 };
709
710 sha: crypto@fc050000 {
711 compatible = "atmel,at91sam9g46-sha";
712 reg = <0xfc050000 0x100>;
713 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
714 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
715 | AT91_XDMAC_DT_PERID(44))>;
716 dma-names = "tx";
717 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
718 clock-names = "sha_clk";
719 };
720
721 hsmc: smc@fc05c000 {
722 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
723 reg = <0xfc05c000 0x1000>;
724 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
725 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
726 #address-cells = <1>;
727 #size-cells = <1>;
728 ranges;
729
730 pmecc: ecc-engine@ffffc070 {
731 compatible = "atmel,sama5d4-pmecc";
732 reg = <0xfc05c070 0x490>,
733 <0xfc05c500 0x100>;
734 };
735 };
736
737 reset_controller: reset-controller@fc068600 {
738 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
739 reg = <0xfc068600 0x10>;
740 clocks = <&clk32k>;
741 };
742
743 shutdown_controller: poweroff@fc068610 {
744 compatible = "atmel,at91sam9x5-shdwc";
745 reg = <0xfc068610 0x10>;
746 clocks = <&clk32k>;
747 };
748
749 pit: timer@fc068630 {
750 compatible = "atmel,at91sam9260-pit";
751 reg = <0xfc068630 0x10>;
752 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
753 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
754 };
755
756 watchdog: watchdog@fc068640 {
757 compatible = "atmel,sama5d4-wdt";
758 reg = <0xfc068640 0x10>;
759 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
760 clocks = <&clk32k>;
761 status = "disabled";
762 };
763
764 clk32k: clock-controller@fc068650 {
765 compatible = "atmel,sama5d4-sckc";
766 reg = <0xfc068650 0x4>;
767 #clock-cells = <0>;
768 clocks = <&slow_xtal>;
769 };
770
771 rtc@fc0686b0 {
772 compatible = "atmel,sama5d4-rtc";
773 reg = <0xfc0686b0 0x30>;
774 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
775 clocks = <&clk32k>;
776 };
777
778 dbgu: serial@fc069000 {
779 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
780 reg = <0xfc069000 0x200>;
781 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
782 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
783 pinctrl-names = "default";
784 pinctrl-0 = <&pinctrl_dbgu>;
785 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
786 clock-names = "usart";
787 status = "disabled";
788 };
789
790
791 pinctrl: pinctrl@fc06a000 {
792 #address-cells = <1>;
793 #size-cells = <1>;
794 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
795 ranges = <0xfc068000 0xfc068000 0x100
796 0xfc06a000 0xfc06a000 0x4000>;
797 /* WARNING: revisit as pin spec has changed */
798 atmel,mux-mask = <
799 /* A B C */
800 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
801 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
802 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
803 0xb003ff00 0x8002a800 0x00000000 /* pioD */
804 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
805 >;
806
807 pioA: gpio@fc06a000 {
808 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
809 reg = <0xfc06a000 0x100>;
810 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
811 #gpio-cells = <2>;
812 gpio-controller;
813 interrupt-controller;
814 #interrupt-cells = <2>;
815 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
816 };
817
818 pioB: gpio@fc06b000 {
819 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
820 reg = <0xfc06b000 0x100>;
821 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
822 #gpio-cells = <2>;
823 gpio-controller;
824 interrupt-controller;
825 #interrupt-cells = <2>;
826 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
827 };
828
829 pioC: gpio@fc06c000 {
830 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
831 reg = <0xfc06c000 0x100>;
832 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
833 #gpio-cells = <2>;
834 gpio-controller;
835 interrupt-controller;
836 #interrupt-cells = <2>;
837 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
838 };
839
840 pioD: gpio@fc068000 {
841 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
842 reg = <0xfc068000 0x100>;
843 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
844 #gpio-cells = <2>;
845 gpio-controller;
846 interrupt-controller;
847 #interrupt-cells = <2>;
848 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
849 };
850
851 pioE: gpio@fc06d000 {
852 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
853 reg = <0xfc06d000 0x100>;
854 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
855 #gpio-cells = <2>;
856 gpio-controller;
857 interrupt-controller;
858 #interrupt-cells = <2>;
859 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
860 };
861
862 /* pinctrl pin settings */
863 adc0 {
864 pinctrl_adc0_adtrg: adc0_adtrg {
865 atmel,pins =
866 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
867 };
868 pinctrl_adc0_ad0: adc0_ad0 {
869 atmel,pins =
870 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
871 };
872 pinctrl_adc0_ad1: adc0_ad1 {
873 atmel,pins =
874 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
875 };
876 pinctrl_adc0_ad2: adc0_ad2 {
877 atmel,pins =
878 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
879 };
880 pinctrl_adc0_ad3: adc0_ad3 {
881 atmel,pins =
882 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
883 };
884 pinctrl_adc0_ad4: adc0_ad4 {
885 atmel,pins =
886 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
887 };
888 };
889
890 dbgu {
891 pinctrl_dbgu: dbgu-0 {
892 atmel,pins =
893 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */
894 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */
895 };
896 };
897
898 ebi {
899 pinctrl_ebi_addr: ebi-addr-0 {
900 atmel,pins =
901 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
902 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
903 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
904 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
905 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
906 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
907 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
908 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
909 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
910 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
911 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
912 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
913 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
914 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
915 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
916 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
917 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
918 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
919 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
920 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
921 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
922 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
923 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE
924 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
925 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
926 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
927 };
928
929 pinctrl_ebi_nand_addr: ebi-addr-1 {
930 atmel,pins =
931 <AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
932 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
933 };
934
935 pinctrl_ebi_cs0: ebi-cs0-0 {
936 atmel,pins =
937 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
938 };
939
940 pinctrl_ebi_cs1: ebi-cs1-0 {
941 atmel,pins =
942 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
943 };
944
945 pinctrl_ebi_cs2: ebi-cs2-0 {
946 atmel,pins =
947 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
948 };
949
950 pinctrl_ebi_cs3: ebi-cs3-0 {
951 atmel,pins =
952 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
953 };
954
955 pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
956 atmel,pins =
957 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE
958 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE
959 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE
960 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE
961 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE
962 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE
963 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE
964 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
965 };
966
967 pinctrl_ebi_data_8_15: ebi-data-msb-0 {
968 atmel,pins =
969 <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE
970 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE
971 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE
972 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE
973 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE
974 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE
975 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE
976 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
977 };
978
979 pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
980 atmel,pins =
981 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
982 };
983
984 pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
985 atmel,pins =
986 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
987 };
988
989 pinctrl_ebi_nwait: ebi-nwait-0 {
990 atmel,pins =
991 <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
992 };
993
994 pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
995 atmel,pins =
996 <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
997 };
998
999 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
1000 atmel,pins =
1001 <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1002 };
1003 };
1004
1005 i2c0 {
1006 pinctrl_i2c0: i2c0-0 {
1007 atmel,pins =
1008 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1009 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1010 };
1011
1012 pinctrl_i2c0_gpio: i2c0-gpio {
1013 atmel,pins =
1014 <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
1015 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
1016 };
1017 };
1018
1019 i2c1 {
1020 pinctrl_i2c1: i2c1-0 {
1021 atmel,pins =
1022 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1023 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1024 };
1025
1026 pinctrl_i2c1_gpio: i2c1-gpio {
1027 atmel,pins =
1028 <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
1029 AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
1030 };
1031 };
1032
1033 i2c2 {
1034 pinctrl_i2c2: i2c2-0 {
1035 atmel,pins =
1036 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1037 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1038 };
1039
1040 pinctrl_i2c2_gpio: i2c2-gpio {
1041 atmel,pins =
1042 <AT91_PIOB 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
1043 AT91_PIOB 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
1044 };
1045 };
1046
1047 isi {
1048 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1049 atmel,pins =
1050 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
1051 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
1052 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
1053 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
1054 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
1055 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
1056 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
1057 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
1058 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
1059 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
1060 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1061 };
1062 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1063 atmel,pins =
1064 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1065 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1066 };
1067 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1068 atmel,pins =
1069 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1070 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1071 };
1072 };
1073
1074 lcd {
1075 pinctrl_lcd_base: lcd-base-0 {
1076 atmel,pins =
1077 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
1078 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
1079 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
1080 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1081 };
1082 pinctrl_lcd_pwm: lcd-pwm-0 {
1083 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
1084 };
1085 pinctrl_lcd_rgb444: lcd-rgb-0 {
1086 atmel,pins =
1087 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1088 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1089 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1090 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1091 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1092 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1093 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1094 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1095 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1096 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1097 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1098 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1099 };
1100 pinctrl_lcd_rgb565: lcd-rgb-1 {
1101 atmel,pins =
1102 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1103 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1104 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1105 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1106 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1107 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1108 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1109 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1110 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1111 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1112 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1113 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1114 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1115 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1116 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1117 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1118 };
1119 pinctrl_lcd_rgb666: lcd-rgb-2 {
1120 atmel,pins =
1121 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1122 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1123 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1124 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1125 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1126 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1127 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1128 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1129 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1130 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1131 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1132 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1133 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1134 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1135 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1136 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1137 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1138 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1139 };
1140 pinctrl_lcd_rgb777: lcd-rgb-3 {
1141 atmel,pins =
1142 /* LCDDAT0 conflicts with TMS */
1143 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1144 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1145 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1146 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1147 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1148 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1149 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1150 /* LCDDAT8 conflicts with TCK */
1151 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1152 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1153 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1154 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1155 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1156 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1157 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1158 /* LCDDAT16 conflicts with NTRST */
1159 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1160 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1161 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1162 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1163 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1164 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1165 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1166 };
1167 pinctrl_lcd_rgb888: lcd-rgb-4 {
1168 atmel,pins =
1169 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1170 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1171 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1172 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1173 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1174 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1175 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1176 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1177 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1178 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1179 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1180 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1181 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1182 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1183 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1184 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1185 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
1186 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1187 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1188 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1189 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1190 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1191 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1192 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1193 };
1194 };
1195
1196 macb0 {
1197 pinctrl_macb0_rmii: macb0_rmii-0 {
1198 atmel,pins =
1199 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1200 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1201 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1202 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1203 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1204 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1205 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1206 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1207 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1208 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1209 >;
1210 };
1211 };
1212
1213 macb1 {
1214 pinctrl_macb1_rmii: macb1_rmii-0 {
1215 atmel,pins =
1216 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */
1217 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */
1218 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */
1219 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */
1220 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */
1221 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */
1222 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */
1223 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */
1224 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */
1225 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */
1226 >;
1227 };
1228 };
1229
1230 mmc0 {
1231 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1232 atmel,pins =
1233 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1234 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */
1235 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */
1236 >;
1237 };
1238 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1239 atmel,pins =
1240 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */
1241 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */
1242 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */
1243 >;
1244 };
1245 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
1246 atmel,pins =
1247 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */
1248 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */
1249 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */
1250 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */
1251 >;
1252 };
1253 };
1254
1255 mmc1 {
1256 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1257 atmel,pins =
1258 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1259 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1260 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1261 >;
1262 };
1263 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1264 atmel,pins =
1265 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1266 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1267 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1268 >;
1269 };
1270 };
1271
1272 nand0 {
1273 pinctrl_nand: nand-0 {
1274 atmel,pins =
1275 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1276 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1277
1278 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1279 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1280
1281 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1282 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1283 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1284 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1285 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1286 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1287 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1288 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1289 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1290 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1291 };
1292 };
1293
1294 spi0 {
1295 pinctrl_spi0: spi0-0 {
1296 atmel,pins =
1297 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1298 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1299 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1300 >;
1301 };
1302 };
1303
1304 ssc0 {
1305 pinctrl_ssc0_tx: ssc0_tx {
1306 atmel,pins =
1307 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1308 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1309 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1310 };
1311
1312 pinctrl_ssc0_rx: ssc0_rx {
1313 atmel,pins =
1314 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1315 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1316 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1317 };
1318 };
1319
1320 ssc1 {
1321 pinctrl_ssc1_tx: ssc1_tx {
1322 atmel,pins =
1323 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1324 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1325 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1326 };
1327
1328 pinctrl_ssc1_rx: ssc1_rx {
1329 atmel,pins =
1330 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1331 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1332 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1333 };
1334 };
1335
1336 spi1 {
1337 pinctrl_spi1: spi1-0 {
1338 atmel,pins =
1339 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */
1340 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */
1341 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */
1342 >;
1343 };
1344 };
1345
1346 spi2 {
1347 pinctrl_spi2: spi2-0 {
1348 atmel,pins =
1349 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */
1350 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */
1351 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */
1352 >;
1353 };
1354 };
1355
1356 uart0 {
1357 pinctrl_uart0: uart0-0 {
1358 atmel,pins =
1359 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1360 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1361 >;
1362 };
1363 };
1364
1365 uart1 {
1366 pinctrl_uart1: uart1-0 {
1367 atmel,pins =
1368 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* RXD */
1369 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* TXD */
1370 >;
1371 };
1372 };
1373
1374 usart0 {
1375 pinctrl_usart0: usart0-0 {
1376 atmel,pins =
1377 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1378 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1379 >;
1380 };
1381 pinctrl_usart0_rts: usart0_rts-0 {
1382 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1383 };
1384 pinctrl_usart0_cts: usart0_cts-0 {
1385 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1386 };
1387 };
1388
1389 usart1 {
1390 pinctrl_usart1: usart1-0 {
1391 atmel,pins =
1392 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1393 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1394 >;
1395 };
1396 pinctrl_usart1_rts: usart1_rts-0 {
1397 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1398 };
1399 pinctrl_usart1_cts: usart1_cts-0 {
1400 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1401 };
1402 };
1403
1404 usart2 {
1405 pinctrl_usart2: usart2-0 {
1406 atmel,pins =
1407 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1408 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD - conflicts with G0_COL, PCK2 */
1409 >;
1410 };
1411 pinctrl_usart2_rts: usart2_rts-0 {
1412 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1413 };
1414 pinctrl_usart2_cts: usart2_cts-0 {
1415 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1416 };
1417 };
1418
1419 usart3 {
1420 pinctrl_usart3: usart3-0 {
1421 atmel,pins =
1422 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1423 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1424 >;
1425 };
1426 };
1427
1428 usart4 {
1429 pinctrl_usart4: usart4-0 {
1430 atmel,pins =
1431 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1432 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1433 >;
1434 };
1435 pinctrl_usart4_rts: usart4_rts-0 {
1436 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1437 };
1438 pinctrl_usart4_cts: usart4_cts-0 {
1439 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1440 };
1441 };
1442 };
1443
1444 aic: interrupt-controller@fc06e000 {
1445 #interrupt-cells = <3>;
1446 compatible = "atmel,sama5d4-aic";
1447 interrupt-controller;
1448 reg = <0xfc06e000 0x200>;
1449 atmel,external-irqs = <56>;
1450 };
1451 };
1452 };
1453};