| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | / { |
| 3 | compatible = "opencores,or1ksim"; |
| 4 | #address-cells = <1>; |
| 5 | #size-cells = <1>; |
| 6 | interrupt-parent = <&pic>; |
| 7 | |
| 8 | aliases { |
| 9 | uart0 = &serial0; |
| 10 | }; |
| 11 | |
| 12 | chosen { |
| 13 | bootargs = "earlycon"; |
| 14 | stdout-path = "uart0:115200"; |
| 15 | }; |
| 16 | |
| 17 | memory@0 { |
| 18 | device_type = "memory"; |
| 19 | reg = <0x00000000 0x02000000>; |
| 20 | }; |
| 21 | |
| 22 | cpus { |
| 23 | #address-cells = <1>; |
| 24 | #size-cells = <0>; |
| 25 | cpu@0 { |
| 26 | compatible = "opencores,or1200-rtlsvn481"; |
| 27 | reg = <0>; |
| 28 | clock-frequency = <20000000>; |
| 29 | }; |
| 30 | cpu@1 { |
| 31 | compatible = "opencores,or1200-rtlsvn481"; |
| 32 | reg = <1>; |
| 33 | clock-frequency = <20000000>; |
| 34 | }; |
| 35 | }; |
| 36 | |
| 37 | ompic: ompic@98000000 { |
| 38 | compatible = "openrisc,ompic"; |
| 39 | reg = <0x98000000 16>; |
| 40 | interrupt-controller; |
| 41 | #interrupt-cells = <0>; |
| 42 | interrupts = <1>; |
| 43 | }; |
| 44 | |
| 45 | /* |
| 46 | * OR1K PIC is built into CPU and accessed via special purpose |
| 47 | * registers. It is not addressable and, hence, has no 'reg' |
| 48 | * property. |
| 49 | */ |
| 50 | pic: pic { |
| 51 | compatible = "opencores,or1k-pic-level"; |
| 52 | #interrupt-cells = <1>; |
| 53 | interrupt-controller; |
| 54 | }; |
| 55 | |
| 56 | serial0: serial@90000000 { |
| 57 | compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; |
| 58 | reg = <0x90000000 0x100>; |
| 59 | interrupts = <2>; |
| 60 | clock-frequency = <20000000>; |
| 61 | }; |
| 62 | |
| 63 | enet0: ethoc@92000000 { |
| 64 | compatible = "opencores,ethoc"; |
| 65 | reg = <0x92000000 0x800>; |
| 66 | interrupts = <4>; |
| 67 | big-endian; |
| 68 | }; |
| 69 | }; |