| Tom Rini | 6bb92fc | 2024-05-20 09:54:58 -0600 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only OR MIT |
| 2 | |
| 3 | #include <dt-bindings/clock/mediatek,mt7981-clk.h> |
| 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 5 | |
| 6 | / { |
| 7 | compatible = "mediatek,mt7981b"; |
| 8 | interrupt-parent = <&gic>; |
| 9 | #address-cells = <2>; |
| 10 | #size-cells = <2>; |
| 11 | |
| 12 | cpus { |
| 13 | #address-cells = <1>; |
| 14 | #size-cells = <0>; |
| 15 | |
| 16 | cpu@0 { |
| 17 | compatible = "arm,cortex-a53"; |
| 18 | reg = <0x0>; |
| 19 | device_type = "cpu"; |
| 20 | enable-method = "psci"; |
| 21 | }; |
| 22 | |
| 23 | cpu@1 { |
| 24 | compatible = "arm,cortex-a53"; |
| 25 | reg = <0x1>; |
| 26 | device_type = "cpu"; |
| 27 | enable-method = "psci"; |
| 28 | }; |
| 29 | }; |
| 30 | |
| 31 | oscillator-40m { |
| 32 | compatible = "fixed-clock"; |
| 33 | clock-frequency = <40000000>; |
| 34 | clock-output-names = "clkxtal"; |
| 35 | #clock-cells = <0>; |
| 36 | }; |
| 37 | |
| 38 | psci { |
| 39 | compatible = "arm,psci-1.0"; |
| 40 | method = "smc"; |
| 41 | }; |
| 42 | |
| 43 | soc { |
| 44 | compatible = "simple-bus"; |
| 45 | ranges; |
| 46 | #address-cells = <2>; |
| 47 | #size-cells = <2>; |
| 48 | |
| 49 | gic: interrupt-controller@c000000 { |
| 50 | compatible = "arm,gic-v3"; |
| 51 | reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| 52 | <0 0x0c080000 0 0x200000>; /* GICR */ |
| 53 | interrupt-parent = <&gic>; |
| 54 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 55 | interrupt-controller; |
| 56 | #interrupt-cells = <3>; |
| 57 | }; |
| 58 | |
| 59 | infracfg: clock-controller@10001000 { |
| 60 | compatible = "mediatek,mt7981-infracfg", "syscon"; |
| 61 | reg = <0 0x10001000 0 0x1000>; |
| 62 | #clock-cells = <1>; |
| 63 | }; |
| 64 | |
| 65 | clock-controller@1001b000 { |
| 66 | compatible = "mediatek,mt7981-topckgen", "syscon"; |
| 67 | reg = <0 0x1001b000 0 0x1000>; |
| 68 | #clock-cells = <1>; |
| 69 | }; |
| 70 | |
| 71 | clock-controller@1001e000 { |
| 72 | compatible = "mediatek,mt7981-apmixedsys"; |
| 73 | reg = <0 0x1001e000 0 0x1000>; |
| 74 | #clock-cells = <1>; |
| 75 | }; |
| 76 | |
| 77 | pwm@10048000 { |
| 78 | compatible = "mediatek,mt7981-pwm"; |
| 79 | reg = <0 0x10048000 0 0x1000>; |
| 80 | clocks = <&infracfg CLK_INFRA_PWM_STA>, |
| 81 | <&infracfg CLK_INFRA_PWM_HCK>, |
| 82 | <&infracfg CLK_INFRA_PWM1_CK>, |
| 83 | <&infracfg CLK_INFRA_PWM2_CK>, |
| 84 | <&infracfg CLK_INFRA_PWM3_CK>; |
| 85 | clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; |
| 86 | #pwm-cells = <2>; |
| 87 | }; |
| 88 | |
| 89 | clock-controller@15000000 { |
| 90 | compatible = "mediatek,mt7981-ethsys", "syscon"; |
| 91 | reg = <0 0x15000000 0 0x1000>; |
| 92 | #clock-cells = <1>; |
| 93 | #reset-cells = <1>; |
| 94 | }; |
| 95 | }; |
| 96 | |
| 97 | timer { |
| 98 | compatible = "arm,armv8-timer"; |
| 99 | interrupt-parent = <&gic>; |
| 100 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 101 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 102 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 103 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| 104 | }; |
| 105 | }; |