Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 0cc64c802dbc39b356cbb9009643258df438600f / . / arch / riscv / dts / k210.dtsi
blob: 84cff51c3691acd64f20d090758b5b8045b7224d [file] [log] [blame]
Sean Andersond11b5822020-06-24 06:41:23 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
4 */
5
6#include <dt-bindings/clock/k210-sysctl.h>
7#include <dt-bindings/mfd/k210-sysctl.h>
8#include <dt-bindings/reset/k210-sysctl.h>
9
10/ {
11 /*
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
13 * wide, and the upper half of all addresses is ignored.
14 */
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "kendryte,k210";
18
19 aliases {
Sean Andersonc6d0ef82020-09-28 10:52:28 -0400[diff] [blame]20 cpu0 = &cpu0;
21 cpu1 = &cpu1;
Sean Andersond11b5822020-06-24 06:41:23 -0400[diff] [blame]22 dma0 = &dmac0;
23 gpio0 = &gpio0;
24 gpio1 = &gpio1_0;
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
28 pinctrl0 = &fpioa;
29 serial0 = &uarths0;
30 serial1 = &uart1;
31 serial2 = &uart2;
32 serial3 = &uart3;
33 spi0 = &spi0;
34 spi1 = &spi1;
35 spi2 = &spi2;
36 spi3 = &spi3;
37 timer0 = &timer0;
38 timer1 = &timer1;
39 timer2 = &timer2;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45 timebase-frequency = <7800000>;
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "kendryte,k210", "sifive,rocket0", "riscv";
49 reg = <0>;
50 riscv,isa = "rv64imafdgc";
51 mmu-type = "sv39";
52 i-cache-block-size = <64>;
53 i-cache-size = <0x8000>;
54 d-cache-block-size = <64>;
55 d-cache-size = <0x8000>;
56 clocks = <&sysclk K210_CLK_CPU>;
57 cpu0_intc: interrupt-controller {
58 #interrupt-cells = <1>;
59 interrupt-controller;
60 compatible = "riscv,cpu-intc";
61 };
62 };
63 cpu1: cpu@1 {
64 device_type = "cpu";
65 compatible = "kendryte,k210", "sifive,rocket0", "riscv";
66 reg = <1>;
67 riscv,isa = "rv64imafdgc";
68 mmu-type = "sv39";
69 i-cache-block-size = <64>;
70 i-cache-size = <0x8000>;
71 d-cache-block-size = <64>;
72 d-cache-size = <0x8000>;
73 clocks = <&sysclk K210_CLK_CPU>;
74 cpu1_intc: interrupt-controller {
75 #interrupt-cells = <1>;
76 interrupt-controller;
77 compatible = "riscv,cpu-intc";
78 };
79 };
80 };
81
82 sram: memory@80000000 {
83 device_type = "memory";
84 compatible = "kendryte,k210-sram";
85 reg = <0x80000000 0x400000>,
86 <0x80400000 0x200000>,
87 <0x80600000 0x200000>;
88 reg-names = "sram0", "sram1", "airam";
89 clocks = <&sysclk K210_CLK_SRAM0>,
90 <&sysclk K210_CLK_SRAM1>,
91 <&sysclk K210_CLK_PLL1>;
92 clock-names = "sram0", "sram1", "airam";
93 };
94
95 reserved-memory {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99
100 ai_reserved: ai@80600000 {
101 reg = <0x80600000 0x200000>;
102 reusable;
103 };
104 };
105
106 clocks {
107 in0: osc {
108 compatible = "fixed-clock";
109 #clock-cells = <0>;
110 clock-frequency = <26000000>;
111 };
112 };
113
114 soc {
115 #address-cells = <1>;
116 #size-cells = <1>;
117 compatible = "kendryte,k210-soc", "simple-bus";
118 ranges;
119 interrupt-parent = <&plic0>;
120
121 debug0: debug@0 {
122 compatible = "kendryte,k210-debug", "riscv,debug";
123 reg = <0x0 0x1000>;
124 };
125
126 rom0: nvmem@1000 {
127 reg = <0x1000 0x1000>;
128 read-only;
129 };
130
Sean Andersonc6d0ef82020-09-28 10:52:28 -0400[diff] [blame]131 clint0: clint@2000000 {
Sean Andersond11b5822020-06-24 06:41:23 -0400[diff] [blame]132 #interrupt-cells = <1>;
133 compatible = "kendryte,k210-clint", "riscv,clint0";
134 reg = <0x2000000 0xC000>;
Sean Andersond11b5822020-06-24 06:41:23 -0400[diff] [blame]135 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
136 <&cpu1_intc 3>, <&cpu1_intc 7>;
Sean Andersonc6d0ef82020-09-28 10:52:28 -0400[diff] [blame]137 clocks = <&sysclk K210_CLK_CLINT>;
Sean Andersond11b5822020-06-24 06:41:23 -0400[diff] [blame]138 };
139
140 plic0: interrupt-controller@C000000 {
141 #interrupt-cells = <1>;
142 compatible = "kendryte,k210-plic", "riscv,plic0";
143 reg = <0xC000000 0x4000000>;
144 interrupt-controller;
145 interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>,
146 <&cpu1_intc 9>, <&cpu1_intc 11>;
147 riscv,ndev = <65>;
148 riscv,max-priority = <7>;
149 };
150
151 uarths0: serial@38000000 {
152 compatible = "kendryte,k210-uarths", "sifive,uart0";
153 reg = <0x38000000 0x1000>;
154 interrupts = <33>;
155 clocks = <&sysclk K210_CLK_CPU>;
156 status = "disabled";
157 };
158
159 gpio0: gpio-controller@38001000 {
160 #interrupt-cells = <2>;
161 #gpio-cells = <2>;
162 compatible = "kendryte,k210-gpiohs", "sifive,gpio0";
163 reg = <0x38001000 0x1000>;
164 interrupt-controller;
165 interrupts = <34 35 36 37 38 39 40 41
166 42 43 44 45 46 47 48 49
167 50 51 52 53 54 55 56 57
168 58 59 60 61 62 63 64 65>;
169 gpio-controller;
170 ngpios = <32>;
171 status = "disabled";
172 };
173
174 kpu0: kpu@40800000 {
175 compatible = "kendryte,k210-kpu";
176 reg = <0x40800000 0xc00000>;
177 interrupts = <25>;
178 clocks = <&sysclk K210_CLK_AI>;
179 memory-region = <&ai_reserved>;
180 status = "disabled";
181 };
182
183 fft0: fft@42000000 {
184 compatible = "kendryte,k210-fft";
185 reg = <0x42000000 0x400000>;
186 interrupts = <26>;
187 clocks = <&sysclk K210_CLK_FFT>;
188 resets = <&sysrst K210_RST_FFT>;
189 status = "disabled";
190 };
191
192 dmac0: dma-controller@50000000 {
193 compatible = "kendryte,k210-dmac", "snps,axi-dma-1.01a";
194 reg = <0x50000000 0x1000>;
195 interrupts = <27 28 29 30 31 32>;
196 clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
197 clock-names = "core-clk", "cfgr-clk";
198 resets = <&sysrst K210_RST_DMA>;
199 dma-channels = <6>;
200 snps,dma-masters = <2>;
201 snps,data-width = <5>;
202 snps,block-size = <0x400000 0x400000 0x400000
203 0x400000 0x400000 0x400000>;
204 snps,axi-max-burst-len = <256>;
205 status = "disabled";
206 };
207
208 apb0: bus@50200000 {
209 #address-cells = <1>;
210 #size-cells = <1>;
211 compatible = "kendryte,k210-apb", "simple-pm-bus";
212 ranges;
213 clocks = <&sysclk K210_CLK_APB0>;
214
215 gpio1: gpio-controller@50200000 {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 compatible = "kendryte,k210-gpio",
219 "snps,dw-apb-gpio";
220 reg = <0x50200000 0x80>;
221 clocks = <&sysclk K210_CLK_GPIO>;
222 resets = <&sysrst K210_RST_GPIO>;
223 status = "disabled";
224
225 gpio1_0: gpio1@0 {
226 #gpio-cells = <2>;
227 #interrupt-cells = <2>;
228 compatible = "snps,dw-apb-gpio-port";
229 reg = <0>;
230 interrupt-controller;
231 interrupts = <23>;
232 gpio-controller;
233 snps,nr-gpios = <8>;
234 };
235 };
236
237 uart1: serial@50210000 {
238 compatible = "kendryte,k210-uart",
239 "snps,dw-apb-uart";
240 reg = <0x50210000 0x100>;
241 interrupts = <11>;
242 clocks = <&sysclk K210_CLK_UART1>;
243 resets = <&sysrst K210_RST_UART1>;
244 reg-io-width = <4>;
245 reg-shift = <2>;
246 dcd-override;
247 dsr-override;
248 cts-override;
249 ri-override;
250 status = "disabled";
251 };
252
253 uart2: serial@50220000 {
254 compatible = "kendryte,k210-uart",
255 "snps,dw-apb-uart";
256 reg = <0x50220000 0x100>;
257 interrupts = <12>;
258 clocks = <&sysclk K210_CLK_UART2>;
259 resets = <&sysrst K210_RST_UART2>;
260 reg-io-width = <4>;
261 reg-shift = <2>;
262 dcd-override;
263 dsr-override;
264 cts-override;
265 ri-override;
266 status = "disabled";
267 };
268
269 uart3: serial@50230000 {
270 compatible = "kendryte,k210-uart",
271 "snps,dw-apb-uart";
272 reg = <0x50230000 0x100>;
273 interrupts = <13>;
274 clocks = <&sysclk K210_CLK_UART3>;
275 resets = <&sysrst K210_RST_UART3>;
276 reg-io-width = <4>;
277 reg-shift = <2>;
278 dcd-override;
279 dsr-override;
280 cts-override;
281 ri-override;
282 status = "disabled";
283 };
284
285 spi2: spi@50240000 {
286 compatible = "kendryte,k120-spislave",
287 "snps,dw-apb-ssi";
288 spi-slave;
289 reg = <0x50240000 0x100>;
290 interrupts = <2>;
291 clocks = <&sysclk K210_CLK_SPI2>;
292 resets = <&sysrst K210_RST_SPI2>;
293 spi-max-frequency = <25000000>;
294 status = "disabled";
295 };
296
297 i2s0: i2s@50250000 {
298 compatible = "kendryte,k210-i2s",
299 "snps,designware-i2s";
300 reg = <0x50250000 0x200>;
301 interrupts = <5>;
302 clocks = <&sysclk K210_CLK_I2S0>;
303 clock-names = "i2sclk";
304 resets = <&sysrst K210_RST_I2S0>;
305 status = "disabled";
306 };
307
308 apu0: sound@520250200 {
309 compatible = "kendryte,k210-apu";
310 reg = <0x50250200 0x200>;
311 status = "disabled";
312 };
313
314 i2s1: i2s@50260000 {
315 compatible = "kendryte,k210-i2s",
316 "snps,designware-i2s";
317 reg = <0x50260000 0x200>;
318 interrupts = <6>;
319 clocks = <&sysclk K210_CLK_I2S1>;
320 clock-names = "i2sclk";
321 resets = <&sysrst K210_RST_I2S1>;
322 status = "disabled";
323 };
324
325 i2s2: i2s@50270000 {
326 compatible = "kendryte,k210-i2s",
327 "snps,designware-i2s";
328 reg = <0x50270000 0x200>;
329 interrupts = <7>;
330 clocks = <&sysclk K210_CLK_I2S2>;
331 clock-names = "i2sclk";
332 resets = <&sysrst K210_RST_I2S2>;
333 status = "disabled";
334 };
335
336 i2c0: i2c@50280000 {
337 compatible = "kendryte,k210-i2c",
338 "snps,designware-i2c";
339 reg = <0x50280000 0x100>;
340 interrupts = <8>;
341 clocks = <&sysclk K210_CLK_I2C0>;
342 resets = <&sysrst K210_RST_I2C0>;
343 status = "disabled";
344 };
345
346 i2c1: i2c@50290000 {
347 compatible = "kendryte,k210-i2c",
348 "snps,designware-i2c";
349 reg = <0x50290000 0x100>;
350 interrupts = <9>;
351 clocks = <&sysclk K210_CLK_I2C1>;
352 resets = <&sysrst K210_RST_I2C1>;
353 status = "disabled";
354 };
355
356 i2c2: i2c@502A0000 {
357 compatible = "kendryte,k210-i2c",
358 "snps,designware-i2c";
359 reg = <0x502A0000 0x100>;
360 interrupts = <10>;
361 clocks = <&sysclk K210_CLK_I2C2>;
362 resets = <&sysrst K210_RST_I2C2>;
363 status = "disabled";
364 };
365
366 fpioa: pinmux@502B0000 {
367 compatible = "kendryte,k210-fpioa";
368 reg = <0x502B0000 0x100>;
369 clocks = <&sysclk K210_CLK_FPIOA>;
370 resets = <&sysrst K210_RST_FPIOA>;
371 status = "disabled";
372 };
373
374 sha256: sha256@502C0000 {
375 compatible = "kendryte,k210-sha256";
376 reg = <0x502C0000 0x100>;
377 clocks = <&sysclk K210_CLK_SHA>;
378 resets = <&sysrst K210_RST_SHA>;
379 status = "disabled";
380 };
381
382 timer0: timer@502D0000 {
383 compatible = "kendryte,k210-timer",
384 "snps,dw-apb-timer";
385 reg = <0x502D0000 0x100>;
386 interrupts = <14 15>;
387 clocks = <&sysclk K210_CLK_TIMER0>;
388 clock-names = "timer";
389 resets = <&sysrst K210_RST_TIMER0>;
390 status = "disabled";
391 };
392
393 timer1: timer@502E0000 {
394 compatible = "kendryte,k210-timer",
395 "snps,dw-apb-timer";
396 reg = <0x502E0000 0x100>;
397 interrupts = <16 17>;
398 clocks = <&sysclk K210_CLK_TIMER1>;
399 clock-names = "timer";
400 resets = <&sysrst K210_RST_TIMER1>;
401 status = "disabled";
402 };
403
404 timer2: timer@502F0000 {
405 compatible = "kendryte,k210-timer",
406 "snps,dw-apb-timer";
407 reg = <0x502F0000 0x100>;
408 interrupts = <18 19>;
409 clocks = <&sysclk K210_CLK_TIMER2>;
410 clock-names = "timer";
411 resets = <&sysrst K210_RST_TIMER2>;
412 status = "disabled";
413 };
414 };
415
416 apb1: bus@50400000 {
417 #address-cells = <1>;
418 #size-cells = <1>;
419 compatible = "kendryte,k210-apb", "simple-pm-bus";
420 ranges;
421 clocks = <&sysclk K210_CLK_APB1>;
422
423 wdt0: watchdog@50400000 {
424 compatible = "kendryte,k210-wdt", "snps,dw-wdt";
425 reg = <0x50400000 0x100>;
426 interrupts = <21>;
427 clocks = <&sysclk K210_CLK_WDT0>;
428 resets = <&sysrst K210_RST_WDT0>;
429 status = "disabled";
430 };
431
432 wdt1: watchdog@50410000 {
433 compatible = "kendryte,k210-wdt", "snps,dw-wdt";
434 reg = <0x50410000 0x100>;
435 interrupts = <22>;
436 clocks = <&sysclk K210_CLK_WDT1>;
437 resets = <&sysrst K210_RST_WDT1>;
438 status = "disabled";
439 };
440
441 otp0: nvmem@50420000 {
442 #address-cells = <1>;
443 #size-cells = <1>;
444 compatible = "kendryte,k210-otp";
445 reg = <0x50420000 0x100>,
446 <0x88000000 0x20000>;
447 reg-names = "reg", "mem";
448 clocks = <&sysclk K210_CLK_ROM>;
449 resets = <&sysrst K210_RST_ROM>;
450 read-only;
451 status = "disabled";
452
453 /* Bootloader */
454 firmware@00000 {
455 reg = <0x00000 0xC200>;
456 };
457
458 /*
459 * config string as described in RISC-V
460 * privileged spec 1.9
461 */
462 config-1-9@1c000 {
463 reg = <0x1C000 0x1000>;
464 };
465
466 /*
467 * Device tree containing only registers,
468 * interrupts, and cpus
469 */
470 fdt@1d000 {
471 reg = <0x1D000 0x2000>;
472 };
473
474 /* CPU/ROM credits */
475 credits@1f000 {
476 reg = <0x1F000 0x1000>;
477 };
478 };
479
480 dvp0: camera@50430000 {
481 compatible = "kendryte,k210-dvp";
482 reg = <0x50430000 0x100>;
483 interrupts = <24>;
484 clocks = <&sysclk K210_CLK_DVP>;
485 resets = <&sysrst K210_RST_DVP>;
486 status = "disabled";
487 };
488
489 sysctl: syscon@50440000 {
490 compatible = "kendryte,k210-sysctl",
491 "syscon", "simple-mfd";
492 reg = <0x50440000 0x100>;
493 reg-io-width = <4>;
494
495 sysclk: clock-controller {
496 #clock-cells = <1>;
497 compatible = "kendryte,k210-clk";
498 clocks = <&in0>;
499 };
500
501 sysrst: reset-controller {
502 compatible = "kendryte,k210-rst",
503 "syscon-reset";
504 #reset-cells = <1>;
505 regmap = <&sysctl>;
506 offset = <K210_SYSCTL_PERI_RESET>;
507 mask = <0x27FFFFFF>;
508 assert-high = <1>;
509 };
510
511 reboot {
512 compatible = "syscon-reboot";
513 regmap = <&sysctl>;
514 offset = <K210_SYSCTL_SOFT_RESET>;
515 mask = <1>;
516 value = <1>;
517 };
518 };
519
520 aes0: aes@50450000 {
521 compatible = "kendryte,k210-aes";
522 reg = <0x50450000 0x100>;
523 clocks = <&sysclk K210_CLK_AES>;
524 resets = <&sysrst K210_RST_AES>;
525 status = "disabled";
526 };
527
528 rtc: rtc@50460000 {
529 compatible = "kendryte,k210-rtc";
530 reg = <0x50460000 0x100>;
531 clocks = <&in0>;
532 resets = <&sysrst K210_RST_RTC>;
533 interrupts = <20>;
534 status = "disabled";
535 };
536 };
537
538 apb2: bus@52000000 {
539 #address-cells = <1>;
540 #size-cells = <1>;
541 compatible = "kendryte,k210-apb", "simple-pm-bus";
542 ranges;
543 clocks = <&sysclk K210_CLK_APB2>;
544
545 spi0: spi@52000000 {
546 #address-cells = <1>;
547 #size-cells = <0>;
548 compatible = "kendryte,k210-spi",
549 "snps,dw-apb-ssi";
550 reg = <0x52000000 0x100>;
551 interrupts = <1>;
552 clocks = <&sysclk K210_CLK_SPI0>;
553 clock-names = "ssi_clk";
554 resets = <&sysrst K210_RST_SPI0>;
555 spi-max-frequency = <25000000>;
556 num-cs = <4>;
557 reg-io-width = <4>;
558 status = "disabled";
559 };
560
561 spi1: spi@53000000 {
562 #address-cells = <1>;
563 #size-cells = <0>;
564 compatible = "kendryte,k210-spi",
565 "snps,dw-apb-ssi";
566 reg = <0x53000000 0x100>;
567 interrupts = <2>;
568 clocks = <&sysclk K210_CLK_SPI1>;
569 clock-names = "ssi_clk";
570 resets = <&sysrst K210_RST_SPI1>;
571 spi-max-frequency = <25000000>;
572 num-cs = <4>;
573 reg-io-width = <4>;
574 status = "disabled";
575 };
576
577 spi3: spi@54000000 {
578 #address-cells = <1>;
579 #size-cells = <0>;
580 compatible = "kendryte,k210-spi",
581 "snps,dw-apb-ssi";
582 reg = <0x54000000 0x200>;
583 interrupts = <4>;
584 clocks = <&sysclk K210_CLK_SPI3>;
585 clock-names = "ssi_clk";
586 resets = <&sysrst K210_RST_SPI3>;
587 /* Could possibly go up to 200 MHz */
588 spi-max-frequency = <100000000>;
589 num-cs = <4>;
590 reg-io-width = <4>;
591 status = "disabled";
592 };
593 };
594 };
595};