| Heiko Schocher | 3c52107 | 2020-02-03 07:43:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * ABB PGGA SUPC5 Device Tree Source |
| 4 | * |
| 5 | * Copyright (C) 2020 Heiko Schocher <hs@denx.de> |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | /dts-v1/; |
| 10 | |
| 11 | #include "km8321.dtsi" |
| 12 | |
| 13 | / { |
| 14 | model = "SUPC5"; |
| 15 | compatible = "ABB,kmpbec8321"; |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | |
| 19 | aliases { |
| 20 | ethernet0 = &enet_piggy2; |
| 21 | serial0 = &serial0; |
| 22 | }; |
| 23 | }; |
| 24 | |
| 25 | &i2c0 { |
| 26 | mux@70 { |
| 27 | compatible = "nxp,pca9547"; |
| 28 | reg = <0x70>; |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <0>; |
| 31 | |
| 32 | i2c@1 { |
| 33 | reg = <1>; |
| 34 | #address-cells = <1>; |
| 35 | #size-cells = <0>; |
| 36 | |
| 37 | /* Inventory EEPROM of the unit itself */ |
| 38 | ivm@50 { |
| 39 | label = "MAIN_CTRL"; |
| 40 | compatible = "dummy"; |
| 41 | reg = <0x50>; |
| 42 | }; |
| 43 | }; |
| 44 | |
| 45 | i2c@2 { |
| 46 | reg = <2>; |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <0>; |
| 49 | |
| 50 | /* Temperature sensors */ |
| 51 | temp@49 { |
| 52 | label = "board"; |
| 53 | compatible = "national,lm75"; |
| 54 | reg = <0x49>; |
| 55 | }; |
| 56 | }; |
| 57 | }; |
| 58 | }; |
| 59 | |
| 60 | &par_io { |
| 61 | /* UCC5 as HDLC controller for ICN */ |
| 62 | pio_ucc5: ucc_pin@04 { |
| 63 | pio-map = < |
| 64 | /* port pin dir open_drain assignment has_irq */ |
| 65 | 2 0 1 0 2 0 /* TxD0 */ |
| 66 | 2 8 2 0 2 0 /* RxD0 */ |
| 67 | 2 29 2 0 2 0 /* CTS */ |
| 68 | 3 30 2 0 1 0 /* ICN CLK */ |
| 69 | >; |
| 70 | }; |
| 71 | |
| 72 | /* UCC4 Piggy Ethernet */ |
| 73 | pio_ucc4: ucc_pin@03 { |
| 74 | pio-map = < |
| 75 | /* port pin dir open_drain assignment has_irq */ |
| 76 | 3 4 3 0 2 0 /* MDIO */ |
| 77 | 3 5 1 0 2 0 /* MDC */ |
| 78 | |
| 79 | 1 18 1 0 1 0 /* TxD0 */ |
| 80 | 1 19 1 0 1 0 /* TxD1 */ |
| 81 | 1 22 2 0 1 0 /* RxD0 */ |
| 82 | 1 23 2 0 1 0 /* RxD1 */ |
| 83 | 1 26 2 0 1 0 /* RX_ER */ |
| 84 | 1 28 2 0 1 0 /* RX_DV */ |
| 85 | 1 30 1 0 1 0 /* TX_EN */ |
| 86 | 1 31 2 0 1 0 /* CRS */ |
| 87 | /* UCC4_RMII_CLK (CLK17) */ |
| 88 | 3 10 2 0 3 0 |
| 89 | >; |
| 90 | }; |
| 91 | |
| 92 | pio_spi: spi_pin@01 { |
| 93 | pio-map = < |
| 94 | /* |
| 95 | * port pin dir open_drain assignment has_irq |
| 96 | * SPI_MOSI (PD0, bi, f3) |
| 97 | */ |
| 98 | 3 0 3 0 1 0 |
| 99 | /* SPI_MISO (PD1, bi, f3) */ |
| 100 | 3 1 3 0 1 0 |
| 101 | /* SPI_CLK (PD2, bi, f3) */ |
| 102 | 3 2 3 0 1 0 |
| 103 | >; |
| 104 | }; |
| 105 | }; |
| 106 | |
| 107 | &spi0 { |
| 108 | pio-handle = <&pio_spi>; |
| 109 | }; |
| 110 | |
| 111 | &localbus { |
| 112 | ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ |
| 113 | 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ |
| 114 | 2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */ |
| 115 | |
| 116 | flash@0,0 { |
| 117 | compatible = "cfi-flash"; |
| 118 | reg = <0 0x00000000 0x04000000>; |
| 119 | bank-width = <2>; |
| 120 | #address-cells = <1>; |
| 121 | #size-cells = <1>; |
| 122 | partition@0 { /* 768KB */ |
| 123 | label = "u-boot"; |
| 124 | reg = <0 0xC0000>; |
| 125 | }; |
| 126 | partition@c0000 { /* 128KB */ |
| 127 | label = "env"; |
| 128 | reg = <0xc0000 0x20000>; |
| 129 | }; |
| 130 | partition@e0000 { /* 128KB */ |
| 131 | label = "envred"; |
| 132 | reg = <0xe0000 0x20000>; |
| 133 | }; |
| 134 | partition@100000 { /* 64512KB */ |
| 135 | label = "ubi0"; |
| 136 | reg = <0x100000 0x3F00000>; |
| 137 | }; |
| 138 | }; |
| 139 | }; |