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git01.mediatek.com / filogic / uboot / 0cb89e7cbd1e53b0350451e596c10433e4c90dfd / . / configs / rockpro64-rk3399_defconfig
blob: 424f21cf15e3a75bc634b8cdb9bd48a04fef4b5f [file] [log] [blame]
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
5CONFIG_SYS_TEXT_BASE=0x00200000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=1
Marcin Juszkiewicz8e1cc412020-06-03 17:15:12 +0200[diff] [blame]7CONFIG_ENV_SIZE=0x8000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]8CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]10CONFIG_ROCKCHIP_RK3399=y
Tom Rini28862bf2019-11-21 08:30:45 -0500[diff] [blame]11CONFIG_TARGET_ROCKPRO64_RK3399=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]12CONFIG_DEBUG_UART_BASE=0xFF1A0000
13CONFIG_DEBUG_UART_CLOCK=24000000
Marcin Juszkiewicz8b5fe242020-06-03 17:15:13 +0200[diff] [blame]14CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]15CONFIG_SPL_SPI=y
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]16CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]17CONFIG_DEBUG_UART=y
Marcin Juszkiewicz5a932fb2020-06-03 17:44:20 +0200[diff] [blame]18CONFIG_USE_PREBOOT=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]19CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]20CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]21CONFIG_MISC_INIT_R=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]22CONFIG_SPL_MAX_SIZE=0x2e000
23CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame^]24CONFIG_SPL_BSS_MAX_SIZE=0x2000
Kever Yang20673542019-08-20 11:47:02 +0800[diff] [blame]25# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]26CONFIG_SPL_STACK_R=y
27CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
Marcin Juszkiewicz8b5fe242020-06-03 17:15:13 +0200[diff] [blame]28CONFIG_SPL_SPI_LOAD=y
Tom Rinic1ca5732019-06-21 10:11:23 -0400[diff] [blame]29CONFIG_TPL=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]30CONFIG_CMD_BOOTZ=y
31CONFIG_CMD_GPT=y
32CONFIG_CMD_MMC=y
Mark Kettenis6870b642020-05-25 11:00:57 +0200[diff] [blame]33CONFIG_CMD_PCI=y
Tom Rini4e852a72020-06-11 13:55:57 -0400[diff] [blame]34CONFIG_CMD_USB=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]35# CONFIG_CMD_SETEXPR is not set
36CONFIG_CMD_TIME=y
37CONFIG_SPL_OF_CONTROL=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]38CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Marcin Juszkiewicz8e1cc412020-06-03 17:15:12 +0200[diff] [blame]39CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]40CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Hugh Cole-Baker99324a12020-11-08 14:00:23 +0000[diff] [blame]41CONFIG_SPL_DM_SEQ_ALIAS=y
Tom Riniffadd402022-04-20 14:48:59 -0400[diff] [blame]42CONFIG_SATA=y
43CONFIG_SCSI_AHCI=y
44CONFIG_AHCI_PCI=y
45CONFIG_SATA_SIL=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]46CONFIG_ROCKCHIP_GPIO=y
47CONFIG_SYS_I2C_ROCKCHIP=y
Hugh Cole-Baker016935e2019-09-09 21:48:17 +0100[diff] [blame]48CONFIG_MISC=y
49CONFIG_ROCKCHIP_EFUSE=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]50CONFIG_MMC_DW=y
51CONFIG_MMC_DW_ROCKCHIP=y
52CONFIG_MMC_SDHCI=y
53CONFIG_MMC_SDHCI_ROCKCHIP=y
Hugh Cole-Baker99324a12020-11-08 14:00:23 +0000[diff] [blame]54CONFIG_SF_DEFAULT_BUS=1
Tom Rini6bd3b142020-02-06 13:42:52 -0500[diff] [blame]55CONFIG_SPI_FLASH_GIGADEVICE=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]56CONFIG_DM_ETH=y
57CONFIG_ETH_DESIGNWARE=y
58CONFIG_GMAC_ROCKCHIP=y
Mark Kettenisf8463d62022-01-22 20:38:11 +0100[diff] [blame]59CONFIG_NVME_PCI=y
Mark Kettenis6870b642020-05-25 11:00:57 +0200[diff] [blame]60CONFIG_PCI=y
Jagan Teki4c9ea092020-07-20 14:53:09 +0530[diff] [blame]61CONFIG_PHY_ROCKCHIP_INNO_USB2=y
62CONFIG_PHY_ROCKCHIP_TYPEC=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]63CONFIG_PMIC_RK8XX=y
64CONFIG_REGULATOR_PWM=y
65CONFIG_REGULATOR_RK8XX=y
66CONFIG_PWM_ROCKCHIP=y
Tom Rini2c7a8d42019-08-14 08:11:27 -0400[diff] [blame]67CONFIG_RAM_RK3399_LPDDR4=y
Tom Rini4e852a72020-06-11 13:55:57 -0400[diff] [blame]68CONFIG_DM_RESET=y
Tom Rinib2e0b322021-01-29 13:56:04 -0500[diff] [blame]69CONFIG_DM_RNG=y
70CONFIG_RNG_ROCKCHIP=y
Tom Riniffadd402022-04-20 14:48:59 -0400[diff] [blame]71CONFIG_SCSI=y
72CONFIG_DM_SCSI=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]73CONFIG_BAUDRATE=1500000
74CONFIG_DEBUG_UART_SHIFT=2
Jagan Tekic0224a42019-12-21 13:24:39 +0530[diff] [blame]75CONFIG_ROCKCHIP_SPI=y
Tom Rini6bd3b142020-02-06 13:42:52 -0500[diff] [blame]76CONFIG_SYSRESET=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]77CONFIG_USB=y
78CONFIG_USB_XHCI_HCD=y
79CONFIG_USB_XHCI_DWC3=y
80CONFIG_USB_EHCI_HCD=y
81CONFIG_USB_EHCI_GENERIC=y
Marcin Juszkiewicz3e240ab2020-05-25 16:44:49 +0200[diff] [blame]82CONFIG_USB_OHCI_HCD=y
83CONFIG_USB_OHCI_GENERIC=y
Jagan Teki4c9ea092020-07-20 14:53:09 +0530[diff] [blame]84CONFIG_USB_DWC3=y
85CONFIG_USB_DWC3_GENERIC=y
Tom Rini63683ef2020-05-26 08:32:25 -0400[diff] [blame]86CONFIG_USB_KEYBOARD=y
Jagan Teki2a2d35f2019-05-17 15:59:40 +0530[diff] [blame]87CONFIG_USB_HOST_ETHER=y
88CONFIG_USB_ETHER_ASIX=y
89CONFIG_USB_ETHER_ASIX88179=y
90CONFIG_USB_ETHER_MCS7830=y
91CONFIG_USB_ETHER_RTL8152=y
92CONFIG_USB_ETHER_SMSC95XX=y
Andrius Štikonas2ba556a2020-04-24 22:03:29 +0100[diff] [blame]93CONFIG_DM_VIDEO=y
Andrius Štikonas2ba556a2020-04-24 22:03:29 +0100[diff] [blame]94CONFIG_DISPLAY=y
95CONFIG_VIDEO_ROCKCHIP=y
96CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Tom Rini63683ef2020-05-26 08:32:25 -0400[diff] [blame]97CONFIG_SPL_TINY_MEMSET=y
98CONFIG_ERRNO_STR=y