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git01.mediatek.com / filogic / uboot / 0c8dea507b6eb88ff851906a504e31ac693182e8 / . / arch / arm / dts / imx8mn-var-som-symphony-u-boot.dtsi
blob: e0caf3179eabe647b7c6bbb7509f07c8e77c1a55 [file] [log] [blame]
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2021 Collabora Ltd.
4 */
5
Adam Ford09e33912022-10-21 19:58:36 -0500[diff] [blame]6#include "imx8mn-u-boot.dtsi"
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]7
8&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]9 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]10};
11
12&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]14};
15
Hugo Villeneuve54553212023-05-25 17:02:28 -0400[diff] [blame]16&eeprom_som {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 eth_mac_address: eth-mac-address@19 {
20 reg = <0x19 0x06>;
21 };
22};
23
24&fec1 {
25 nvmem-cells = <&eth_mac_address>;
26 nvmem-cell-names = "mac-address";
27};
28
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]29&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]31};
32
33&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]35};
36
37&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]39};
40
41&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]43};
44
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]45&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]47};
48
49&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]51};
52
53&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]55};
56
57&pinctrl_uart4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]59};
60
61&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]63};
64
65&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]67};
68
69&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]71};
72
73&uart4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]75};
76
77&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]79};
80
81&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -0300[diff] [blame]83};
Hugo Villeneuved3cdac42023-05-25 17:02:25 -0400[diff] [blame]84
85&eeprom_som {
86 bootph-pre-ram;
87};