Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 0c4354e05576e81a53c79e536410741a0c6c0425 / . / board / nvidia / nyan-big / nyan-big.c
blob: 06a36f8ed3871920702999ebc2958feff7ba2284 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Allen Martina142ac72014-12-04 06:36:30 -0700[diff] [blame]2/*
3 * (C) Copyright 2014
4 * NVIDIA Corporation <www.nvidia.com>
Allen Martina142ac72014-12-04 06:36:30 -0700[diff] [blame]5 */
6
7#include <common.h>
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]8#include <dm.h>
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]9#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]10#include <log.h>
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]11#include <asm/gpio.h>
Simon Glass899af8e2015-06-05 14:39:43 -0600[diff] [blame]12#include <asm/io.h>
Allen Martina142ac72014-12-04 06:36:30 -0700[diff] [blame]13#include <asm/arch/pinmux.h>
Simon Glass899af8e2015-06-05 14:39:43 -0600[diff] [blame]14#include <asm/arch/clock.h>
15#include <asm/arch/mc.h>
16#include <asm/arch-tegra/clk_rst.h>
17#include <asm/arch-tegra/pmc.h>
Simon Glassdbd79542020-05-10 11:40:11 -0600[diff] [blame]18#include <linux/delay.h>
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]19#include <power/as3722.h>
20#include <power/pmic.h>
Allen Martina142ac72014-12-04 06:36:30 -0700[diff] [blame]21#include "pinmux-config-nyan-big.h"
22
23/*
24 * Routine: pinmux_init
25 * Description: Do individual peripheral pinmux configs
26 */
27void pinmux_init(void)
28{
29 gpio_config_table(nyan_big_gpio_inits,
30 ARRAY_SIZE(nyan_big_gpio_inits));
31
32 pinmux_config_pingrp_table(nyan_big_pingrps,
33 ARRAY_SIZE(nyan_big_pingrps));
34
35 pinmux_config_drvgrp_table(nyan_big_drvgrps,
36 ARRAY_SIZE(nyan_big_drvgrps));
37}
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]38
39int tegra_board_id(void)
40{
Stephen Warren7f20bb22016-05-12 12:07:39 -0600[diff] [blame]41 static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
42 TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
43 -1};
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]44
45 gpio_claim_vector(vector, "board_id%d");
46 return gpio_get_values_as_int(vector);
47}
48
49int tegra_lcd_pmic_init(int board_id)
50{
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]51 struct udevice *dev;
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]52 int ret;
53
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]54 ret = uclass_get_device_by_driver(UCLASS_PMIC,
Simon Glass65130cd2020-12-28 20:34:56 -0700[diff] [blame]55 DM_DRIVER_GET(pmic_as3722), &dev);
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]56 if (ret) {
57 debug("%s: Failed to find PMIC\n", __func__);
58 return ret;
59 }
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]60
61 if (board_id == 0)
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]62 pmic_reg_write(dev, 0x00, 0x3c);
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]63 else
Simon Glassb3d2ed32017-07-25 08:30:12 -0600[diff] [blame]64 pmic_reg_write(dev, 0x00, 0x50);
65 pmic_reg_write(dev, 0x12, 0x10);
66 pmic_reg_write(dev, 0x0c, 0x07);
67 pmic_reg_write(dev, 0x20, 0x10);
Simon Glass5ec924c2015-04-14 21:03:29 -0600[diff] [blame]68
69 return 0;
70}
Simon Glass899af8e2015-06-05 14:39:43 -0600[diff] [blame]71
72/* Setup required information for Linux kernel */
73static void setup_kernel_info(void)
74{
75 struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
76
77 /* The kernel graphics driver needs this region locked down */
78 writel(0, &mc->mc_video_protect_bom);
79 writel(0, &mc->mc_video_protect_size_mb);
80 writel(1, &mc->mc_video_protect_reg_ctrl);
81}
82
83/*
84 * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
85 * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
86 * Otherwise reading AHUB devices will hang when the kernel boots.
87 */
88static void enable_required_clocks(void)
89{
90 static enum periph_id ids[] = {
91 PERIPH_ID_I2S0,
92 PERIPH_ID_I2S1,
93 PERIPH_ID_I2S2,
94 PERIPH_ID_I2S3,
95 PERIPH_ID_I2S4,
96 PERIPH_ID_AUDIO,
97 PERIPH_ID_APBIF,
98 PERIPH_ID_DAM0,
99 PERIPH_ID_DAM1,
100 PERIPH_ID_DAM2,
101 PERIPH_ID_AMX0,
102 PERIPH_ID_AMX1,
103 PERIPH_ID_ADX0,
104 PERIPH_ID_ADX1,
105 PERIPH_ID_SPDIF,
106 PERIPH_ID_AFC0,
107 PERIPH_ID_AFC1,
108 PERIPH_ID_AFC2,
109 PERIPH_ID_AFC3,
110 PERIPH_ID_AFC4,
111 PERIPH_ID_AFC5,
112 PERIPH_ID_EXTPERIPH1
113 };
114 int i;
115
116 for (i = 0; i < ARRAY_SIZE(ids); i++)
117 clock_enable(ids[i]);
118 udelay(2);
119 for (i = 0; i < ARRAY_SIZE(ids); i++)
120 reset_set_enable(ids[i], 0);
121}
122
123int nvidia_board_init(void)
124{
125 clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
Simon Glassf4253352019-04-01 13:38:38 -0700[diff] [blame]126 clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000);
Simon Glass899af8e2015-06-05 14:39:43 -0600[diff] [blame]127
128 /* For external MAX98090 audio codec */
129 clock_external_output(1);
130 setup_kernel_info();
131 enable_required_clocks();
132
133 return 0;
134}