Meenakshi Aggarwal | 8a03b0d | 2020-12-04 20:17:28 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2020 NXP |
| 4 | * |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <env.h> |
| 9 | #include <fdt_support.h> |
| 10 | #include <hwconfig.h> |
| 11 | #include <command.h> |
| 12 | #include <log.h> |
| 13 | #include <net.h> |
| 14 | #include <netdev.h> |
| 15 | #include <malloc.h> |
| 16 | #include <fsl_mdio.h> |
| 17 | #include <miiphy.h> |
| 18 | #include <phy.h> |
| 19 | #include <fm_eth.h> |
| 20 | #include <asm/io.h> |
| 21 | #include <exports.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 22 | #include <asm/global_data.h> |
Meenakshi Aggarwal | 8a03b0d | 2020-12-04 20:17:28 +0530 | [diff] [blame] | 23 | #include <asm/arch/fsl_serdes.h> |
| 24 | #include <fsl-mc/fsl_mc.h> |
| 25 | #include <fsl-mc/ldpaa_wriop.h> |
| 26 | #include <linux/libfdt.h> |
| 27 | |
| 28 | #include "../common/qixis.h" |
| 29 | |
| 30 | DECLARE_GLOBAL_DATA_PTR; |
| 31 | |
| 32 | #ifndef CONFIG_DM_ETH |
| 33 | #define EMI_NONE 0 |
| 34 | #define EMI1 1 /* Mdio Bus 1 */ |
| 35 | #define EMI2 2 /* Mdio Bus 2 */ |
| 36 | |
| 37 | #if defined(CONFIG_FSL_MC_ENET) |
| 38 | enum io_slot { |
| 39 | IO_SLOT_NONE = 0, |
| 40 | IO_SLOT_1, |
| 41 | IO_SLOT_2, |
| 42 | IO_SLOT_3, |
| 43 | IO_SLOT_4, |
| 44 | IO_SLOT_5, |
| 45 | IO_SLOT_6, |
| 46 | IO_SLOT_7, |
| 47 | IO_SLOT_8, |
| 48 | EMI1_RGMII1, |
| 49 | EMI1_RGMII2, |
| 50 | IO_SLOT_MAX |
| 51 | }; |
| 52 | |
| 53 | struct lx2162a_qds_mdio { |
| 54 | enum io_slot ioslot : 4; |
| 55 | u8 realbusnum : 4; |
| 56 | struct mii_dev *realbus; |
| 57 | }; |
| 58 | |
| 59 | /* structure explaining the phy configuration on 8 lanes of a serdes*/ |
| 60 | struct serdes_phy_config { |
| 61 | u8 serdes; /* serdes protocol */ |
| 62 | struct phy_config { |
| 63 | u8 dpmacid; |
| 64 | /* -1 terminated array */ |
| 65 | int phy_address[WRIOP_MAX_PHY_NUM + 1]; |
| 66 | u8 mdio_bus; |
| 67 | enum io_slot ioslot; |
| 68 | } phy_config[SRDS_MAX_LANES]; |
| 69 | }; |
| 70 | |
| 71 | /* Table defining the phy configuration on 8 lanes of a serdes. |
| 72 | * Various assumptions have been made while defining this table. |
| 73 | * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII |
| 74 | * card is being used for dpmac 3-4. (X-M12-XFI could also have been used) |
| 75 | * And also that this card is connected to IO Slot 1 (could have been connected |
| 76 | * to any of the 8 IO slots (IO slot 1 - IO slot 8)). |
| 77 | * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card |
| 78 | * used in serdes1 protocol 19 (could have selected MDIO 2) |
| 79 | * To override these settings "dpmac" environment variable can be used after |
| 80 | * defining "dpmac_override" in hwconfig environment variable. |
| 81 | * This table has limited serdes protocol entries. It can be expanded as per |
| 82 | * requirement. |
| 83 | */ |
| 84 | /***************************************************************** |
| 85 | *| SERDES_1 PROTOCOL | IO_SLOT | CARD | |
| 86 | ****************************************************************** |
| 87 | *| 2 | IO_SLOT_1 | M4-PCIE-SGMII | |
| 88 | *| 3 | IO_SLOT_1 | M11-USXGMII | |
| 89 | *| 15 | IO_SLOT_1 | M13-25G | |
| 90 | *| 17 | IO_SLOT_1 | M13-25G | |
| 91 | *| 18 | IO_SLOT_1 | M11-USXGMII | |
| 92 | *| | IO_SLOT_6 | M13-25G | |
| 93 | *| 20 | IO_SLOT_1 | M7-40G | |
| 94 | ***************************************************************** |
| 95 | */ |
| 96 | static const struct serdes_phy_config serdes1_phy_config[] = { |
| 97 | {1, {} }, |
| 98 | {2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1}, |
| 99 | EMI1, IO_SLOT_1}, |
| 100 | {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1}, |
| 101 | EMI1, IO_SLOT_1}, |
| 102 | {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1}, |
| 103 | EMI1, IO_SLOT_1}, |
| 104 | {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1}, |
| 105 | EMI1, IO_SLOT_1} } }, |
| 106 | {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1}, |
| 107 | EMI1, IO_SLOT_1}, |
| 108 | {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1}, |
| 109 | EMI1, IO_SLOT_1}, |
| 110 | {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1}, |
| 111 | EMI1, IO_SLOT_1}, |
| 112 | {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1}, |
| 113 | EMI1, IO_SLOT_1} } }, |
| 114 | {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, |
| 115 | EMI1, IO_SLOT_1}, |
| 116 | {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, |
| 117 | EMI1, IO_SLOT_1} } }, |
| 118 | {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, |
| 119 | EMI1, IO_SLOT_1}, |
| 120 | {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, |
| 121 | EMI1, IO_SLOT_1}, |
| 122 | {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, |
| 123 | EMI1, IO_SLOT_1}, |
| 124 | {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, |
| 125 | EMI1, IO_SLOT_1} } }, |
| 126 | {18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1}, |
| 127 | EMI1, IO_SLOT_1}, |
| 128 | {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1}, |
| 129 | EMI1, IO_SLOT_1}, |
| 130 | {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, |
| 131 | EMI1, IO_SLOT_6}, |
| 132 | {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, |
| 133 | EMI1, IO_SLOT_6} } }, |
| 134 | {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1}, |
| 135 | EMI1, IO_SLOT_1} } } |
| 136 | }; |
| 137 | |
| 138 | /***************************************************************** |
| 139 | *| SERDES_2 PROTOCOL | IO_SLOT | CARD | |
| 140 | ****************************************************************** |
| 141 | *| 2 | IO_SLOT_7 | M4-PCIE-SGMII | |
| 142 | *| | IO_SLOT_8 | M4-PCIE-SGMII | |
| 143 | *| 3 | IO_SLOT_7 | M4-PCIE-SGMII | |
| 144 | *| | IO_SLOT_8 | M4-PCIE-SGMII | |
| 145 | *| 5 | IO_SLOT_7 | M4-PCIE-SGMII | |
| 146 | *| 10 | IO_SLOT_7 | M4-PCIE-SGMII | |
| 147 | *| | IO_SLOT_8 | M4-PCIE-SGMII | |
| 148 | *| 11 | IO_SLOT_7 | M4-PCIE-SGMII | |
| 149 | *| | IO_SLOT_8 | M4-PCIE-SGMII | |
| 150 | *| 12 | IO_SLOT_7 | M4-PCIE-SGMII | |
| 151 | *| | IO_SLOT_8 | M4-PCIE-SGMII | |
| 152 | ****************************************************************** |
| 153 | */ |
| 154 | static const struct serdes_phy_config serdes2_phy_config[] = { |
| 155 | {2, {} }, |
| 156 | {3, {} }, |
| 157 | {5, {} }, |
| 158 | {10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1}, |
| 159 | EMI1, IO_SLOT_7}, |
| 160 | {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, |
| 161 | EMI1, IO_SLOT_7}, |
| 162 | {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, |
| 163 | EMI1, IO_SLOT_7}, |
| 164 | {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, |
| 165 | EMI1, IO_SLOT_7} } }, |
| 166 | {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, |
| 167 | EMI1, IO_SLOT_7}, |
| 168 | {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, |
| 169 | EMI1, IO_SLOT_7}, |
| 170 | {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, |
| 171 | EMI1, IO_SLOT_7}, |
| 172 | {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1}, |
| 173 | EMI1, IO_SLOT_8}, |
| 174 | {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1}, |
| 175 | EMI1, IO_SLOT_8}, |
| 176 | {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1}, |
| 177 | EMI1, IO_SLOT_8} } }, |
| 178 | {12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1}, |
| 179 | EMI1, IO_SLOT_7}, |
| 180 | {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, |
| 181 | EMI1, IO_SLOT_7}, |
| 182 | {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, |
| 183 | EMI1, IO_SLOT_7}, |
| 184 | {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, |
| 185 | EMI1, IO_SLOT_7} } } |
| 186 | }; |
| 187 | |
| 188 | static inline |
| 189 | const struct phy_config *get_phy_config(u8 serdes, |
| 190 | const struct serdes_phy_config *table, |
| 191 | u8 table_size) |
| 192 | { |
| 193 | int i; |
| 194 | |
| 195 | for (i = 0; i < table_size; i++) { |
| 196 | if (table[i].serdes == serdes) |
| 197 | return table[i].phy_config; |
| 198 | } |
| 199 | |
| 200 | return NULL; |
| 201 | } |
| 202 | |
| 203 | /* BRDCFG4 controls EMI routing for the board. |
| 204 | * Bits Function |
| 205 | * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V): |
| 206 | * EMI1 00= On-board PHY #1 |
| 207 | * 01= On-board PHY #2 |
| 208 | * 10= (reserved) |
| 209 | * 11= Slots 1..8 multiplexer and translator. |
| 210 | * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V): |
| 211 | * EMI1X 000= Slot #1 |
| 212 | * 001= Slot #2 |
| 213 | * 010= Slot #3 |
| 214 | * 011= Slot #4 |
| 215 | * 100= Slot #5 |
| 216 | * 101= Slot #6 |
| 217 | * 110= Slot #7 |
| 218 | * 111= Slot #8 |
| 219 | * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2): |
| 220 | * EMI2 000= Slot #1 (secondary EMI) |
| 221 | * 001= Slot #2 (secondary EMI) |
| 222 | * 010= Slot #3 (secondary EMI) |
| 223 | * 011= Slot #4 (secondary EMI) |
| 224 | * 100= Slot #5 (secondary EMI) |
| 225 | * 101= Slot #6 (secondary EMI) |
| 226 | * 110= Slot #7 (secondary EMI) |
| 227 | * 111= Slot #8 (secondary EMI) |
| 228 | */ |
| 229 | static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot) |
| 230 | { |
| 231 | switch (realbusnum) { |
| 232 | case EMI1: |
| 233 | switch (ioslot) { |
| 234 | case EMI1_RGMII1: |
| 235 | return 0; |
| 236 | case EMI1_RGMII2: |
| 237 | return 0x40; |
| 238 | default: |
| 239 | return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0); |
| 240 | } |
| 241 | break; |
| 242 | case EMI2: |
| 243 | return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT); |
| 244 | default: |
| 245 | return -1; |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv) |
| 250 | { |
| 251 | u8 brdcfg4, mux_val, reg; |
| 252 | |
| 253 | brdcfg4 = QIXIS_READ(brdcfg[4]); |
| 254 | reg = brdcfg4; |
| 255 | mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot); |
| 256 | |
| 257 | switch (priv->realbusnum) { |
| 258 | case EMI1: |
| 259 | brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK; |
| 260 | brdcfg4 |= mux_val; |
| 261 | break; |
| 262 | case EMI2: |
| 263 | brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK; |
| 264 | brdcfg4 |= mux_val; |
| 265 | break; |
| 266 | } |
| 267 | |
| 268 | if (brdcfg4 ^ reg) |
| 269 | QIXIS_WRITE(brdcfg[4], brdcfg4); |
| 270 | } |
| 271 | |
| 272 | static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr, |
| 273 | int devad, int regnum) |
| 274 | { |
| 275 | struct lx2162a_qds_mdio *priv = bus->priv; |
| 276 | |
| 277 | lx2162a_qds_mux_mdio(priv); |
| 278 | |
| 279 | return priv->realbus->read(priv->realbus, addr, devad, regnum); |
| 280 | } |
| 281 | |
| 282 | static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, |
| 283 | int regnum, u16 value) |
| 284 | { |
| 285 | struct lx2162a_qds_mdio *priv = bus->priv; |
| 286 | |
| 287 | lx2162a_qds_mux_mdio(priv); |
| 288 | |
| 289 | return priv->realbus->write(priv->realbus, addr, devad, regnum, value); |
| 290 | } |
| 291 | |
| 292 | static int lx2162a_qds_mdio_reset(struct mii_dev *bus) |
| 293 | { |
| 294 | struct lx2162a_qds_mdio *priv = bus->priv; |
| 295 | |
| 296 | return priv->realbus->reset(priv->realbus); |
| 297 | } |
| 298 | |
| 299 | static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot) |
| 300 | { |
| 301 | struct lx2162a_qds_mdio *pmdio; |
| 302 | struct mii_dev *bus; |
| 303 | /*should be within MDIO_NAME_LEN*/ |
| 304 | char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1"; |
| 305 | |
| 306 | if (realbusnum == EMI2) { |
| 307 | if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) { |
| 308 | printf("invalid ioslot %d\n", ioslot); |
| 309 | return NULL; |
| 310 | } |
| 311 | } else if (realbusnum == EMI1) { |
| 312 | if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) { |
| 313 | printf("invalid ioslot %d\n", ioslot); |
| 314 | return NULL; |
| 315 | } |
| 316 | } else { |
| 317 | printf("not supported real mdio bus %d\n", realbusnum); |
| 318 | return NULL; |
| 319 | } |
| 320 | |
| 321 | if (ioslot == EMI1_RGMII1) |
| 322 | strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1"); |
| 323 | else if (ioslot == EMI1_RGMII2) |
| 324 | strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2"); |
| 325 | else |
| 326 | sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d", |
| 327 | realbusnum, ioslot); |
| 328 | bus = miiphy_get_dev_by_name(dummy_mdio_name); |
| 329 | |
| 330 | if (bus) |
| 331 | return bus; |
| 332 | |
| 333 | bus = mdio_alloc(); |
| 334 | if (!bus) { |
| 335 | printf("Failed to allocate %s bus\n", dummy_mdio_name); |
| 336 | return NULL; |
| 337 | } |
| 338 | |
| 339 | pmdio = malloc(sizeof(*pmdio)); |
| 340 | if (!pmdio) { |
| 341 | printf("Failed to allocate %s private data\n", dummy_mdio_name); |
| 342 | free(bus); |
| 343 | return NULL; |
| 344 | } |
| 345 | |
| 346 | switch (realbusnum) { |
| 347 | case EMI1: |
| 348 | pmdio->realbus = |
| 349 | miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); |
| 350 | break; |
| 351 | case EMI2: |
| 352 | pmdio->realbus = |
| 353 | miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); |
| 354 | break; |
| 355 | } |
| 356 | |
| 357 | if (!pmdio->realbus) { |
| 358 | printf("No real mdio bus num %d found\n", realbusnum); |
| 359 | free(bus); |
| 360 | free(pmdio); |
| 361 | return NULL; |
| 362 | } |
| 363 | |
| 364 | pmdio->realbusnum = realbusnum; |
| 365 | pmdio->ioslot = ioslot; |
| 366 | bus->read = lx2162a_qds_mdio_read; |
| 367 | bus->write = lx2162a_qds_mdio_write; |
| 368 | bus->reset = lx2162a_qds_mdio_reset; |
| 369 | strcpy(bus->name, dummy_mdio_name); |
| 370 | bus->priv = pmdio; |
| 371 | |
| 372 | if (!mdio_register(bus)) |
| 373 | return bus; |
| 374 | |
| 375 | printf("No bus with name %s\n", dummy_mdio_name); |
| 376 | free(bus); |
| 377 | free(pmdio); |
| 378 | return NULL; |
| 379 | } |
| 380 | |
| 381 | static inline void do_phy_config(const struct phy_config *phy_config) |
| 382 | { |
| 383 | struct mii_dev *bus; |
| 384 | int i, phy_num, phy_address; |
| 385 | |
| 386 | for (i = 0; i < SRDS_MAX_LANES; i++) { |
| 387 | if (!phy_config[i].dpmacid) |
| 388 | continue; |
| 389 | |
| 390 | for (phy_num = 0; |
| 391 | phy_num < ARRAY_SIZE(phy_config[i].phy_address); |
| 392 | phy_num++) { |
| 393 | phy_address = phy_config[i].phy_address[phy_num]; |
| 394 | if (phy_address == -1) |
| 395 | break; |
| 396 | wriop_set_phy_address(phy_config[i].dpmacid, |
| 397 | phy_num, phy_address); |
| 398 | } |
| 399 | /*Register the muxing front-ends to the MDIO buses*/ |
| 400 | bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus, |
| 401 | phy_config[i].ioslot); |
| 402 | if (!bus) |
| 403 | printf("could not get bus for mdio %d ioslot %d\n", |
| 404 | phy_config[i].mdio_bus, |
| 405 | phy_config[i].ioslot); |
| 406 | else |
| 407 | wriop_set_mdio(phy_config[i].dpmacid, bus); |
| 408 | } |
| 409 | } |
| 410 | |
| 411 | static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid, |
| 412 | char *env_dpmac) |
| 413 | { |
| 414 | const char *ret; |
| 415 | size_t len; |
| 416 | u8 realbusnum, ioslot; |
| 417 | struct mii_dev *bus; |
| 418 | int phy_num; |
| 419 | char *phystr = "phy00"; |
| 420 | |
| 421 | /*search phy in dpmac arg*/ |
| 422 | for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) { |
| 423 | sprintf(phystr, "phy%d", phy_num + 1); |
| 424 | ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac); |
| 425 | if (!ret) { |
| 426 | /*look for phy instead of phy1*/ |
| 427 | if (!phy_num) |
| 428 | ret = hwconfig_subarg_f(arg_dpmacid, "phy", |
| 429 | &len, env_dpmac); |
| 430 | if (!ret) |
| 431 | continue; |
| 432 | } |
| 433 | |
| 434 | if (len != 4 || strncmp(ret, "0x", 2)) |
| 435 | printf("invalid phy format in %s variable.\n" |
| 436 | "specify phy%d for %s in hex format e.g. 0x12\n", |
| 437 | env_dpmac, phy_num + 1, arg_dpmacid); |
| 438 | else |
| 439 | wriop_set_phy_address(dpmac, phy_num, |
Simon Glass | 3ff49ec | 2021-07-24 09:03:29 -0600 | [diff] [blame] | 440 | hextoul(ret, NULL)); |
Meenakshi Aggarwal | 8a03b0d | 2020-12-04 20:17:28 +0530 | [diff] [blame] | 441 | } |
| 442 | |
| 443 | /*search mdio in dpmac arg*/ |
| 444 | ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac); |
| 445 | if (ret) |
| 446 | realbusnum = *ret - '0'; |
| 447 | else |
| 448 | realbusnum = EMI_NONE; |
| 449 | |
| 450 | if (realbusnum) { |
| 451 | /*search io in dpmac arg*/ |
| 452 | ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac); |
| 453 | if (ret) |
| 454 | ioslot = *ret - '0'; |
| 455 | else |
| 456 | ioslot = IO_SLOT_NONE; |
| 457 | /*Register the muxing front-ends to the MDIO buses*/ |
| 458 | bus = lx2162a_qds_mdio_init(realbusnum, ioslot); |
| 459 | if (!bus) |
| 460 | printf("could not get bus for mdio %d ioslot %d\n", |
| 461 | realbusnum, ioslot); |
| 462 | else |
| 463 | wriop_set_mdio(dpmac, bus); |
| 464 | } |
| 465 | } |
| 466 | |
| 467 | #endif |
| 468 | #endif /* !CONFIG_DM_ETH */ |
| 469 | |
| 470 | int board_eth_init(struct bd_info *bis) |
| 471 | { |
| 472 | #ifndef CONFIG_DM_ETH |
| 473 | #if defined(CONFIG_FSL_MC_ENET) |
| 474 | struct memac_mdio_info mdio_info; |
| 475 | struct memac_mdio_controller *regs; |
| 476 | int i; |
| 477 | const char *ret; |
| 478 | char *env_dpmac; |
| 479 | char dpmacid[] = "dpmac00", srds[] = "00_00_00"; |
| 480 | size_t len; |
| 481 | struct mii_dev *bus; |
| 482 | const struct phy_config *phy_config; |
| 483 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 484 | u32 srds_s1, srds_s2; |
| 485 | |
| 486 | srds_s1 = in_le32(&gur->rcwsr[28]) & |
| 487 | FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; |
| 488 | srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; |
| 489 | |
| 490 | srds_s2 = in_le32(&gur->rcwsr[28]) & |
| 491 | FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; |
| 492 | srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; |
| 493 | |
| 494 | sprintf(srds, "%d_%d", srds_s1, srds_s2); |
| 495 | |
| 496 | regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; |
| 497 | mdio_info.regs = regs; |
| 498 | mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; |
| 499 | |
| 500 | /*Register the EMI 1*/ |
| 501 | fm_memac_mdio_init(bis, &mdio_info); |
| 502 | |
| 503 | regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; |
| 504 | mdio_info.regs = regs; |
| 505 | mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; |
| 506 | |
| 507 | /*Register the EMI 2*/ |
| 508 | fm_memac_mdio_init(bis, &mdio_info); |
| 509 | |
| 510 | /* "dpmac" environment variable can be used after |
| 511 | * defining "dpmac_override" in hwconfig environment variable. |
| 512 | */ |
| 513 | if (hwconfig("dpmac_override")) { |
| 514 | env_dpmac = env_get("dpmac"); |
| 515 | if (env_dpmac) { |
| 516 | ret = hwconfig_arg_f("srds", &len, env_dpmac); |
| 517 | if (ret) { |
| 518 | if (strncmp(ret, srds, strlen(srds))) { |
| 519 | printf("SERDES configuration changed.\n" |
| 520 | "previous: %.*s, current: %s.\n" |
| 521 | "update dpmac variable.\n", |
| 522 | (int)len, ret, srds); |
| 523 | } |
| 524 | } else { |
| 525 | printf("SERDES configuration not found.\n" |
| 526 | "Please add srds:%s in dpmac variable\n", |
| 527 | srds); |
| 528 | } |
| 529 | |
| 530 | for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { |
| 531 | /* Look for dpmac1 to dpmac24(current max) arg |
| 532 | * in dpmac environment variable |
| 533 | */ |
| 534 | sprintf(dpmacid, "dpmac%d", i); |
| 535 | ret = hwconfig_arg_f(dpmacid, &len, env_dpmac); |
| 536 | if (ret) |
| 537 | do_dpmac_config(i, dpmacid, env_dpmac); |
| 538 | } |
| 539 | } else { |
| 540 | printf("Warning: environment dpmac not found.\n" |
| 541 | "DPAA network interfaces may not work\n"); |
| 542 | } |
| 543 | } else { |
| 544 | /*Look for phy config for serdes1 in phy config table*/ |
| 545 | phy_config = get_phy_config(srds_s1, serdes1_phy_config, |
| 546 | ARRAY_SIZE(serdes1_phy_config)); |
| 547 | if (!phy_config) { |
| 548 | printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n", |
| 549 | __func__, srds_s1); |
| 550 | } else { |
| 551 | do_phy_config(phy_config); |
| 552 | } |
| 553 | phy_config = get_phy_config(srds_s2, serdes2_phy_config, |
| 554 | ARRAY_SIZE(serdes2_phy_config)); |
| 555 | if (!phy_config) { |
| 556 | printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n", |
| 557 | __func__, srds_s2); |
| 558 | } else { |
| 559 | do_phy_config(phy_config); |
| 560 | } |
| 561 | } |
| 562 | |
| 563 | if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) { |
| 564 | wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1); |
| 565 | bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1); |
| 566 | if (!bus) |
| 567 | printf("could not get bus for RGMII1\n"); |
| 568 | else |
| 569 | wriop_set_mdio(WRIOP1_DPMAC17, bus); |
| 570 | } |
| 571 | |
| 572 | if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) { |
| 573 | wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2); |
| 574 | bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2); |
| 575 | if (!bus) |
| 576 | printf("could not get bus for RGMII2\n"); |
| 577 | else |
| 578 | wriop_set_mdio(WRIOP1_DPMAC18, bus); |
| 579 | } |
| 580 | |
| 581 | cpu_eth_init(bis); |
| 582 | #endif /* CONFIG_FMAN_ENET */ |
| 583 | #endif /* !CONFIG_DM_ETH */ |
| 584 | |
| 585 | #ifdef CONFIG_PHY_AQUANTIA |
| 586 | /* |
| 587 | * Export functions to be used by AQ firmware |
| 588 | * upload application |
| 589 | */ |
| 590 | gd->jt->strcpy = strcpy; |
| 591 | gd->jt->mdelay = mdelay; |
| 592 | gd->jt->mdio_get_current_dev = mdio_get_current_dev; |
| 593 | gd->jt->phy_find_by_mask = phy_find_by_mask; |
| 594 | gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; |
| 595 | gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; |
| 596 | #endif |
| 597 | |
| 598 | #ifdef CONFIG_DM_ETH |
| 599 | return 0; |
| 600 | #else |
| 601 | return pci_eth_init(bis); |
| 602 | #endif |
| 603 | } |
| 604 | |
| 605 | #if defined(CONFIG_RESET_PHY_R) |
| 606 | void reset_phy(void) |
| 607 | { |
| 608 | #if defined(CONFIG_FSL_MC_ENET) |
| 609 | mc_env_boot(); |
| 610 | #endif |
| 611 | } |
| 612 | #endif /* CONFIG_RESET_PHY_R */ |
| 613 | |
| 614 | #ifndef CONFIG_DM_ETH |
| 615 | #if defined(CONFIG_FSL_MC_ENET) |
| 616 | int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle) |
| 617 | { |
| 618 | int offset; |
| 619 | int ret; |
| 620 | char dpmac_str[] = "dpmacs@00"; |
| 621 | const char *phy_string; |
| 622 | |
| 623 | offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs"); |
| 624 | |
| 625 | if (offset < 0) |
| 626 | offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs"); |
| 627 | |
| 628 | if (offset < 0) { |
| 629 | printf("dpmacs node not found in device tree\n"); |
| 630 | return offset; |
| 631 | } |
| 632 | |
| 633 | sprintf(dpmac_str, "dpmac@%x", dpmac_id); |
| 634 | debug("dpmac_str = %s\n", dpmac_str); |
| 635 | |
| 636 | offset = fdt_subnode_offset(fdt, offset, dpmac_str); |
| 637 | if (offset < 0) { |
| 638 | printf("%s node not found in device tree\n", dpmac_str); |
| 639 | return offset; |
| 640 | } |
| 641 | |
| 642 | phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL); |
| 643 | if (is_backplane_mode(phy_string)) { |
| 644 | /* Backplane KR mode: skip fixups */ |
| 645 | printf("Interface %d in backplane KR mode\n", dpmac_id); |
| 646 | return 0; |
| 647 | } |
| 648 | |
| 649 | ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle); |
| 650 | if (ret) |
| 651 | printf("%d@%s %d\n", __LINE__, __func__, ret); |
| 652 | |
| 653 | phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id)); |
| 654 | ret = fdt_setprop_string(fdt, offset, "phy-connection-type", |
| 655 | phy_string); |
| 656 | if (ret) |
| 657 | printf("%d@%s %d\n", __LINE__, __func__, ret); |
| 658 | |
| 659 | return ret; |
| 660 | } |
| 661 | |
| 662 | int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset) |
| 663 | { |
| 664 | char mdio_ioslot_str[] = "mdio@00"; |
| 665 | struct lx2162a_qds_mdio *priv; |
| 666 | u64 reg; |
| 667 | u32 phandle; |
| 668 | int offset, mux_val; |
| 669 | |
| 670 | /*Test if the MDIO bus is real mdio bus or muxing front end ?*/ |
| 671 | if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO", |
| 672 | strlen("LX2162A_QDS_MDIO"))) |
| 673 | return -1; |
| 674 | |
| 675 | /*Get the real MDIO bus num and ioslot info from bus's priv data*/ |
| 676 | priv = mii_dev->priv; |
| 677 | |
| 678 | debug("real_bus_num = %d, ioslot = %d\n", |
| 679 | priv->realbusnum, priv->ioslot); |
| 680 | |
| 681 | if (priv->realbusnum == EMI1) |
| 682 | reg = CONFIG_SYS_FSL_WRIOP1_MDIO1; |
| 683 | else |
| 684 | reg = CONFIG_SYS_FSL_WRIOP1_MDIO2; |
| 685 | |
| 686 | offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg); |
| 687 | if (offset < 0) { |
| 688 | printf("mdio@%llx node not found in device tree\n", reg); |
| 689 | return offset; |
| 690 | } |
| 691 | |
| 692 | phandle = fdt_get_phandle(fdt, offset); |
| 693 | phandle = cpu_to_fdt32(phandle); |
| 694 | offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus", |
| 695 | &phandle, 4); |
| 696 | if (offset < 0) { |
| 697 | printf("mdio-mux-%d node not found in device tree\n", |
| 698 | priv->realbusnum == EMI1 ? 1 : 2); |
| 699 | return offset; |
| 700 | } |
| 701 | |
| 702 | mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot); |
| 703 | if (priv->realbusnum == EMI1) |
| 704 | mux_val >>= BRDCFG4_EMI1SEL_SHIFT; |
| 705 | else |
| 706 | mux_val >>= BRDCFG4_EMI2SEL_SHIFT; |
| 707 | sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val); |
| 708 | |
| 709 | offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str); |
| 710 | if (offset < 0) { |
| 711 | printf("%s node not found in device tree\n", mdio_ioslot_str); |
| 712 | return offset; |
| 713 | } |
| 714 | |
| 715 | return offset; |
| 716 | } |
| 717 | |
| 718 | int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset, |
| 719 | struct phy_device *phy_dev, int phandle) |
| 720 | { |
| 721 | char phy_node_name[] = "ethernet-phy@00"; |
| 722 | char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,"; |
| 723 | int ret; |
| 724 | |
| 725 | sprintf(phy_node_name, "ethernet-phy@%x", phyaddr); |
| 726 | debug("phy_node_name = %s\n", phy_node_name); |
| 727 | |
| 728 | *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name); |
| 729 | if (*subnodeoffset <= 0) { |
| 730 | printf("Could not add subnode %s inside node %s err = %s\n", |
| 731 | phy_node_name, fdt_get_name(fdt, offset, NULL), |
| 732 | fdt_strerror(*subnodeoffset)); |
| 733 | return *subnodeoffset; |
| 734 | } |
| 735 | |
| 736 | sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,", |
| 737 | phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF); |
| 738 | debug("phy_id_compatible_str %s\n", phy_id_compatible_str); |
| 739 | |
| 740 | ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible", |
| 741 | phy_id_compatible_str); |
| 742 | if (ret) { |
| 743 | printf("%d@%s %d\n", __LINE__, __func__, ret); |
| 744 | goto out; |
| 745 | } |
| 746 | |
| 747 | if (phy_dev->is_c45) { |
| 748 | ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible", |
| 749 | "ethernet-phy-ieee802.3-c45"); |
| 750 | if (ret) { |
| 751 | printf("%d@%s %d\n", __LINE__, __func__, ret); |
| 752 | goto out; |
| 753 | } |
| 754 | } else { |
| 755 | ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible", |
| 756 | "ethernet-phy-ieee802.3-c22"); |
| 757 | if (ret) { |
| 758 | printf("%d@%s %d\n", __LINE__, __func__, ret); |
| 759 | goto out; |
| 760 | } |
| 761 | } |
| 762 | |
| 763 | ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr); |
| 764 | if (ret) { |
| 765 | printf("%d@%s %d\n", __LINE__, __func__, ret); |
| 766 | goto out; |
| 767 | } |
| 768 | |
| 769 | ret = fdt_set_phandle(fdt, *subnodeoffset, phandle); |
| 770 | if (ret) { |
| 771 | printf("%d@%s %d\n", __LINE__, __func__, ret); |
| 772 | goto out; |
| 773 | } |
| 774 | |
| 775 | out: |
| 776 | if (ret) |
| 777 | fdt_del_node(fdt, *subnodeoffset); |
| 778 | |
| 779 | return ret; |
| 780 | } |
| 781 | |
| 782 | #define is_rgmii(dpmac_id) \ |
| 783 | wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID |
| 784 | |
| 785 | int fdt_fixup_board_phy(void *fdt) |
| 786 | { |
| 787 | int fpga_offset, offset, subnodeoffset; |
| 788 | struct mii_dev *mii_dev; |
| 789 | struct list_head *mii_devs, *entry; |
| 790 | int ret, dpmac_id, phandle, i; |
| 791 | struct phy_device *phy_dev; |
| 792 | char ethname[ETH_NAME_LEN]; |
| 793 | phy_interface_t phy_iface; |
| 794 | |
| 795 | ret = 0; |
| 796 | /* we know FPGA is connected to i2c0, therefore search path directly, |
| 797 | * instead of compatible property, as it saves time |
| 798 | */ |
| 799 | fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga"); |
| 800 | |
| 801 | if (fpga_offset < 0) |
| 802 | fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga"); |
| 803 | |
| 804 | if (fpga_offset < 0) { |
| 805 | printf("i2c@2000000/fpga node not found in device tree\n"); |
| 806 | return fpga_offset; |
| 807 | } |
| 808 | |
| 809 | phandle = fdt_alloc_phandle(fdt); |
| 810 | mii_devs = mdio_get_list_head(); |
| 811 | |
| 812 | list_for_each(entry, mii_devs) { |
| 813 | mii_dev = list_entry(entry, struct mii_dev, link); |
| 814 | debug("mii_dev name : %s\n", mii_dev->name); |
| 815 | offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset); |
| 816 | if (offset < 0) |
| 817 | continue; |
| 818 | |
| 819 | // Look for phy devices attached to MDIO bus muxing front end |
| 820 | // and create their entries with compatible being the device id |
| 821 | for (i = 0; i < PHY_MAX_ADDR; i++) { |
| 822 | phy_dev = mii_dev->phymap[i]; |
| 823 | if (!phy_dev) |
| 824 | continue; |
| 825 | |
| 826 | // TODO: use sscanf instead of loop |
| 827 | dpmac_id = WRIOP1_DPMAC1; |
| 828 | while (dpmac_id < NUM_WRIOP_PORTS) { |
| 829 | phy_iface = wriop_get_enet_if(dpmac_id); |
| 830 | snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", |
| 831 | dpmac_id, |
| 832 | phy_string_for_interface(phy_iface)); |
| 833 | if (strcmp(ethname, phy_dev->dev->name) == 0) |
| 834 | break; |
| 835 | dpmac_id++; |
| 836 | } |
| 837 | if (dpmac_id == NUM_WRIOP_PORTS) |
| 838 | continue; |
| 839 | |
| 840 | if ((dpmac_id == 17 || dpmac_id == 18) && |
| 841 | is_rgmii(dpmac_id)) |
| 842 | continue; |
| 843 | |
| 844 | ret = fdt_create_phy_node(fdt, offset, i, |
| 845 | &subnodeoffset, |
| 846 | phy_dev, phandle); |
| 847 | if (ret) |
| 848 | break; |
| 849 | |
| 850 | ret = fdt_fixup_dpmac_phy_handle(fdt, |
| 851 | dpmac_id, phandle); |
| 852 | if (ret) { |
| 853 | fdt_del_node(fdt, subnodeoffset); |
| 854 | break; |
| 855 | } |
| 856 | /* calculate offset again as new node addition may have |
| 857 | * changed offset; |
| 858 | */ |
| 859 | offset = fdt_get_ioslot_offset(fdt, mii_dev, |
| 860 | fpga_offset); |
| 861 | phandle++; |
| 862 | } |
| 863 | |
| 864 | if (ret) |
| 865 | break; |
| 866 | } |
| 867 | |
| 868 | return ret; |
| 869 | } |
| 870 | #endif // CONFIG_FSL_MC_ENET |
| 871 | #endif |
| 872 | |
| 873 | #if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) |
| 874 | |
| 875 | /* Structure to hold SERDES protocols supported in case of |
| 876 | * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). |
| 877 | * |
| 878 | * @serdes_block: the index of the SERDES block |
| 879 | * @serdes_protocol: the decimal value of the protocol supported |
| 880 | * @dts_needed: DTS notes describing the current configuration are needed |
| 881 | * |
| 882 | * When dts_needed is true, the board_fit_config_name_match() function |
| 883 | * will try to exactly match the current configuration of the block with a DTS |
| 884 | * name provided. |
| 885 | */ |
| 886 | static struct serdes_configuration { |
| 887 | u8 serdes_block; |
| 888 | u32 serdes_protocol; |
| 889 | bool dts_needed; |
| 890 | } supported_protocols[] = { |
| 891 | /* Serdes block #1 */ |
| 892 | {1, 2, true}, |
| 893 | {1, 3, true}, |
| 894 | {1, 15, true}, |
| 895 | {1, 17, true}, |
| 896 | {1, 18, true}, |
| 897 | {1, 20, true}, |
| 898 | |
| 899 | /* Serdes block #2 */ |
| 900 | {2, 2, false}, |
| 901 | {2, 3, false}, |
| 902 | {2, 5, false}, |
| 903 | {2, 10, false}, |
| 904 | {2, 11, true}, |
| 905 | {2, 12, true}, |
| 906 | }; |
| 907 | |
| 908 | #define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) |
| 909 | |
| 910 | static bool protocol_supported(u8 serdes_block, u32 protocol) |
| 911 | { |
| 912 | struct serdes_configuration serdes_conf; |
| 913 | int i; |
| 914 | |
| 915 | for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { |
| 916 | serdes_conf = supported_protocols[i]; |
| 917 | if (serdes_conf.serdes_block == serdes_block && |
| 918 | serdes_conf.serdes_protocol == protocol) |
| 919 | return true; |
| 920 | } |
| 921 | |
| 922 | return false; |
| 923 | } |
| 924 | |
| 925 | static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) |
| 926 | { |
| 927 | struct serdes_configuration serdes_conf; |
| 928 | int i; |
| 929 | |
| 930 | for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { |
| 931 | serdes_conf = supported_protocols[i]; |
| 932 | if (serdes_conf.serdes_block == serdes_block && |
| 933 | serdes_conf.serdes_protocol == protocol) { |
| 934 | if (serdes_conf.dts_needed == true) |
| 935 | sprintf(str, "%u", protocol); |
| 936 | else |
| 937 | sprintf(str, "x"); |
| 938 | return; |
| 939 | } |
| 940 | } |
| 941 | } |
| 942 | |
| 943 | int board_fit_config_name_match(const char *name) |
| 944 | { |
| 945 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 946 | u32 rcw_status = in_le32(&gur->rcwsr[28]); |
| 947 | char srds_s1_str[2], srds_s2_str[2]; |
| 948 | u32 srds_s1, srds_s2; |
| 949 | char expected_dts[100]; |
| 950 | |
| 951 | srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; |
| 952 | srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; |
| 953 | |
| 954 | srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; |
| 955 | srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; |
| 956 | |
| 957 | /* Check for supported protocols. The default DTS will be used |
| 958 | * in this case |
| 959 | */ |
| 960 | if (!protocol_supported(1, srds_s1) || |
| 961 | !protocol_supported(2, srds_s2)) |
| 962 | return -1; |
| 963 | |
| 964 | get_str_protocol(1, srds_s1, srds_s1_str); |
| 965 | get_str_protocol(2, srds_s2, srds_s2_str); |
| 966 | |
| 967 | sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s", |
| 968 | srds_s1_str, srds_s2_str); |
| 969 | |
| 970 | if (!strcmp(name, expected_dts)) |
| 971 | return 0; |
| 972 | |
| 973 | return -1; |
| 974 | } |
| 975 | #endif |