blob: e3502eb1d1924692655ed526dddde3219f56eebb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ashish Kumar227b4bc2017-08-31 16:12:54 +05302/*
3 * Copyright 2017 NXP
Ashish Kumar227b4bc2017-08-31 16:12:54 +05304 */
5
6#ifndef __LS1088AQDS_QIXIS_H__
7#define __LS1088AQDS_QIXIS_H__
8
9/* Definitions of QIXIS Registers for LS1088AQDS */
10
11/* SYSCLK */
12#define QIXIS_SYSCLK_66 0x0
13#define QIXIS_SYSCLK_83 0x1
14#define QIXIS_SYSCLK_100 0x2
15#define QIXIS_SYSCLK_125 0x3
16#define QIXIS_SYSCLK_133 0x4
17#define QIXIS_SYSCLK_150 0x5
18#define QIXIS_SYSCLK_160 0x6
19#define QIXIS_SYSCLK_166 0x7
20
21/* DDRCLK */
22#define QIXIS_DDRCLK_66 0x0
23#define QIXIS_DDRCLK_100 0x1
24#define QIXIS_DDRCLK_125 0x2
25#define QIXIS_DDRCLK_133 0x3
26
27/* BRDCFG2 - SD clock*/
28#define QIXIS_SDCLK1_100 0x0
29#define QIXIS_SDCLK1_125 0x1
30#define QIXIS_SDCLK1_165 0x2
31#define QIXIS_SDCLK1_100_SP 0x3
32
Ashish Kumar1ef4c772017-08-31 16:12:55 +053033#define BRDCFG4_EMISEL_MASK 0xE0
34#define BRDCFG4_EMISEL_SHIFT 5
35#define BRDCFG9_SFPTX_MASK 0x10
36#define BRDCFG9_SFPTX_SHIFT 4
37
Yangbo Lu1d879532017-11-27 15:40:17 +080038/* Definitions of QIXIS Registers for LS1088ARDB */
39
40/* BRDCFG5 */
41#define BRDCFG5_SPISDHC_MASK 0x0C
42#define BRDCFG5_FORCE_SD 0x08
43
Chuanhua Han26b39ef2019-08-01 16:36:57 +080044/* Definitions of QIXIS Registers for LS1088AQDS */
45
46/* BRDCFG4 */
47#define BRDCFG4_USBOSC_MASK 0x01
48#define BRDCFG4_SPI 0x01
49
50/* BRDCFG5 */
51#define BRDCFG5_SPR_MASK 0x0f
52#define BRDCFG5_SPI_ON_BOARD 0x0a
53#define BRDCFG5_SPI_OFF_BOARD 0x0f
54
Ashish Kumar227b4bc2017-08-31 16:12:54 +053055#endif