| Jagan Teki | 2ee11ff | 2018-08-02 15:43:02 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2018 Amarula Solutions. |
| 4 | * Author: Jagan Teki <jagan@amarulasolutions.com> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <clk-uclass.h> |
| 9 | #include <dm.h> |
| 10 | #include <errno.h> |
| 11 | #include <asm/arch/ccu.h> |
| 12 | #include <dt-bindings/clock/sun8i-h3-ccu.h> |
| 13 | #include <dt-bindings/reset/sun8i-h3-ccu.h> |
| 14 | |
| 15 | static struct ccu_clk_gate h3_gates[] = { |
| 16 | [CLK_BUS_OTG] = GATE(0x060, BIT(23)), |
| 17 | [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), |
| 18 | [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), |
| 19 | [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)), |
| 20 | [CLK_BUS_EHCI3] = GATE(0x060, BIT(27)), |
| 21 | [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), |
| 22 | [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)), |
| 23 | [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), |
| 24 | [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)), |
| 25 | |
| 26 | [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), |
| 27 | [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), |
| 28 | [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)), |
| 29 | [CLK_USB_PHY3] = GATE(0x0cc, BIT(11)), |
| 30 | [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)), |
| 31 | [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), |
| 32 | [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)), |
| 33 | [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)), |
| 34 | }; |
| 35 | |
| 36 | static struct ccu_reset h3_resets[] = { |
| 37 | [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), |
| 38 | [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), |
| 39 | [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), |
| 40 | [RST_USB_PHY3] = RESET(0x0cc, BIT(3)), |
| 41 | |
| 42 | [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), |
| 43 | [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)), |
| 44 | [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)), |
| 45 | [RST_BUS_EHCI2] = RESET(0x2c0, BIT(26)), |
| 46 | [RST_BUS_EHCI3] = RESET(0x2c0, BIT(27)), |
| 47 | [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)), |
| 48 | [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)), |
| 49 | [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)), |
| 50 | [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)), |
| 51 | }; |
| 52 | |
| 53 | static const struct ccu_desc h3_ccu_desc = { |
| 54 | .gates = h3_gates, |
| 55 | .resets = h3_resets, |
| 56 | }; |
| 57 | |
| 58 | static int h3_clk_bind(struct udevice *dev) |
| 59 | { |
| 60 | return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets)); |
| 61 | } |
| 62 | |
| 63 | static const struct udevice_id h3_ccu_ids[] = { |
| 64 | { .compatible = "allwinner,sun8i-h3-ccu", |
| 65 | .data = (ulong)&h3_ccu_desc }, |
| 66 | { .compatible = "allwinner,sun50i-h5-ccu", |
| 67 | .data = (ulong)&h3_ccu_desc }, |
| 68 | { } |
| 69 | }; |
| 70 | |
| 71 | U_BOOT_DRIVER(clk_sun8i_h3) = { |
| 72 | .name = "sun8i_h3_ccu", |
| 73 | .id = UCLASS_CLK, |
| 74 | .of_match = h3_ccu_ids, |
| 75 | .priv_auto_alloc_size = sizeof(struct ccu_priv), |
| 76 | .ops = &sunxi_clk_ops, |
| 77 | .probe = sunxi_clk_probe, |
| 78 | .bind = h3_clk_bind, |
| 79 | }; |