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git01.mediatek.com / filogic / uboot / 0c078eac03d47981cdf8053a40274f1f97691684 / . / arch / arm / include / asm / arch-ls102xa / ns_access.h
blob: b53f69951ad0ccdd031d6750538b0be3342f6f55 [file] [log] [blame]
Xiubo Li54de0652014-11-21 17:40:58 +0800[diff] [blame]1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __FSL_NS_ACCESS_H_
8#define __FSL_NS_ACCESS_H_
9
10enum csu_cslx_access {
11 CSU_NS_SUP_R = 0x08,
12 CSU_NS_SUP_W = 0x80,
13 CSU_NS_SUP_RW = 0x88,
14 CSU_NS_USER_R = 0x04,
15 CSU_NS_USER_W = 0x40,
16 CSU_NS_USER_RW = 0x44,
17 CSU_S_SUP_R = 0x02,
18 CSU_S_SUP_W = 0x20,
19 CSU_S_SUP_RW = 0x22,
20 CSU_S_USER_R = 0x01,
21 CSU_S_USER_W = 0x10,
22 CSU_S_USER_RW = 0x11,
23 CSU_ALL_RW = 0xff,
24};
25
26enum csu_cslx_ind {
27 CSU_CSLX_PCIE2_IO = 0,
28 CSU_CSLX_PCIE1_IO,
29 CSU_CSLX_MG2TPR_IP,
30 CSU_CSLX_IFC_MEM,
31 CSU_CSLX_OCRAM,
32 CSU_CSLX_GIC,
33 CSU_CSLX_PCIE1,
34 CSU_CSLX_OCRAM2,
35 CSU_CSLX_QSPI_MEM,
36 CSU_CSLX_PCIE2,
37 CSU_CSLX_SATA,
38 CSU_CSLX_USB3,
39 CSU_CSLX_SERDES = 32,
40 CSU_CSLX_QDMA,
41 CSU_CSLX_LPUART2,
42 CSU_CSLX_LPUART1,
43 CSU_CSLX_LPUART4,
44 CSU_CSLX_LPUART3,
45 CSU_CSLX_LPUART6,
46 CSU_CSLX_LPUART5,
47 CSU_CSLX_DSPI2 = 40,
48 CSU_CSLX_DSPI1,
49 CSU_CSLX_QSPI,
50 CSU_CSLX_ESDHC,
51 CSU_CSLX_2D_ACE,
52 CSU_CSLX_IFC,
53 CSU_CSLX_I2C1,
54 CSU_CSLX_USB2,
55 CSU_CSLX_I2C3,
56 CSU_CSLX_I2C2,
57 CSU_CSLX_DUART2 = 50,
58 CSU_CSLX_DUART1,
59 CSU_CSLX_WDT2,
60 CSU_CSLX_WDT1,
61 CSU_CSLX_EDMA,
62 CSU_CSLX_SYS_CNT,
63 CSU_CSLX_DMA_MUX2,
64 CSU_CSLX_DMA_MUX1,
65 CSU_CSLX_DDR,
66 CSU_CSLX_QUICC,
67 CSU_CSLX_DCFG_CCU_RCPM = 60,
68 CSU_CSLX_SECURE_BOOTROM,
69 CSU_CSLX_SFP,
70 CSU_CSLX_TMU,
71 CSU_CSLX_SECURE_MONITOR,
72 CSU_CSLX_RESERVED0,
73 CSU_CSLX_ETSEC1,
74 CSU_CSLX_SEC5_5,
75 CSU_CSLX_ETSEC3,
76 CSU_CSLX_ETSEC2,
77 CSU_CSLX_GPIO2 = 70,
78 CSU_CSLX_GPIO1,
79 CSU_CSLX_GPIO4,
80 CSU_CSLX_GPIO3,
81 CSU_CSLX_PLATFORM_CONT,
82 CSU_CSLX_CSU,
83 CSU_CSLX_ASRC,
84 CSU_CSLX_SPDIF,
85 CSU_CSLX_FLEXCAN2,
86 CSU_CSLX_FLEXCAN1,
87 CSU_CSLX_FLEXCAN4 = 80,
88 CSU_CSLX_FLEXCAN3,
89 CSU_CSLX_SAI2,
90 CSU_CSLX_SAI1,
91 CSU_CSLX_SAI4,
92 CSU_CSLX_SAI3,
93 CSU_CSLX_FTM2,
94 CSU_CSLX_FTM1,
95 CSU_CSLX_FTM4,
96 CSU_CSLX_FTM3,
97 CSU_CSLX_FTM6 = 90,
98 CSU_CSLX_FTM5,
99 CSU_CSLX_FTM8,
100 CSU_CSLX_FTM7,
101 CSU_CSLX_COP_DCSR,
102 CSU_CSLX_EPU,
103 CSU_CSLX_GDI,
104 CSU_CSLX_DDI,
105 CSU_CSLX_RESERVED1,
106 CSU_CSLX_USB3_PHY = 117,
107 CSU_CSLX_RESERVED2,
108 CSU_CSLX_MAX,
109};
110
111struct csu_ns_dev {
112 unsigned long ind;
113 uint32_t val;
114};
115
116void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
117
118#endif