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git01.mediatek.com / filogic / uboot / 0c078eac03d47981cdf8053a40274f1f97691684 / . / arch / arm / include / asm / arch-fsl-lsch3 / immap_lsch3.h
blob: dd11ef79c8c2f2f97a38f35d98b9f4d9f07050a1 [file] [log] [blame]
York Suna84cd722014-06-23 15:15:54 -0700[diff] [blame]1/*
2 * LayerScape Internal Memory Map
3 *
4 * Copyright 2014 Freescale Semiconductor, Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __ARCH_FSL_LSCH3_IMMAP_H
10#define __ARCH_FSL_LSCH3_IMMAP_H_
11
12/* This is chassis generation 3 */
13
14struct sys_info {
15 unsigned long freq_processor[CONFIG_MAX_CPUS];
16 unsigned long freq_systembus;
17 unsigned long freq_ddrbus;
York Sun1ecab782015-01-06 13:18:49 -0800[diff] [blame]18 unsigned long freq_ddrbus2;
York Suna84cd722014-06-23 15:15:54 -0700[diff] [blame]19 unsigned long freq_localbus;
20 unsigned long freq_qe;
21#ifdef CONFIG_SYS_DPAA_FMAN
22 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
23#endif
24#ifdef CONFIG_SYS_DPAA_QBMAN
25 unsigned long freq_qman;
26#endif
27#ifdef CONFIG_SYS_DPAA_PME
28 unsigned long freq_pme;
29#endif
30};
31
32/* Global Utilities Block */
33struct ccsr_gur {
34 u32 porsr1; /* POR status 1 */
35 u32 porsr2; /* POR status 2 */
36 u8 res_008[0x20-0x8];
37 u32 gpporcr1; /* General-purpose POR configuration */
38 u32 gpporcr2; /* General-purpose POR configuration 2 */
39 u32 dcfg_fusesr; /* Fuse status register */
40 u32 gpporcr3;
41 u32 gpporcr4;
42 u8 res_034[0x70-0x34];
43 u32 devdisr; /* Device disable control */
44 u32 devdisr2; /* Device disable control 2 */
45 u32 devdisr3; /* Device disable control 3 */
46 u32 devdisr4; /* Device disable control 4 */
47 u32 devdisr5; /* Device disable control 5 */
48 u32 devdisr6; /* Device disable control 6 */
49 u32 devdisr7; /* Device disable control 7 */
50 u8 res_08c[0x90-0x8c];
51 u32 coredisru; /* uppper portion for support of 64 cores */
52 u32 coredisrl; /* lower portion for support of 64 cores */
53 u8 res_098[0xa0-0x98];
54 u32 pvr; /* Processor version */
55 u32 svr; /* System version */
56 u32 mvr; /* Manufacturing version */
57 u8 res_0ac[0x100-0xac];
58 u32 rcwsr[32]; /* Reset control word status */
59
60#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
61#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
62#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
63#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
York Sun1ecab782015-01-06 13:18:49 -0800[diff] [blame]64#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
65#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
York Suna84cd722014-06-23 15:15:54 -0700[diff] [blame]66 u8 res_180[0x200-0x180];
67 u32 scratchrw[32]; /* Scratch Read/Write */
68 u8 res_280[0x300-0x280];
69 u32 scratchw1r[4]; /* Scratch Read (Write once) */
70 u8 res_310[0x400-0x310];
71 u32 bootlocptrl; /* Boot location pointer low-order addr */
72 u32 bootlocptrh; /* Boot location pointer high-order addr */
73 u8 res_408[0x500-0x408];
74 u8 res_500[0x740-0x500]; /* add more registers when needed */
75 u32 tp_ityp[64]; /* Topology Initiator Type Register */
76 struct {
77 u32 upper;
78 u32 lower;
79 } tp_cluster[3]; /* Core Cluster n Topology Register */
80 u8 res_858[0x1000-0x858];
81};
82
83#define TP_ITYP_AV 0x00000001 /* Initiator available */
84#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
85#define TP_ITYP_TYPE_ARM 0x0
86#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
87#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
88#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
89#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
90#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
91#define TY_ITYP_VER_A7 0x1
92#define TY_ITYP_VER_A53 0x2
93#define TY_ITYP_VER_A57 0x3
94
95#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
96#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
97#define TP_INIT_PER_CLUSTER 4
98
99struct ccsr_clk_cluster_group {
100 struct {
101 u8 res_00[0x10];
102 u32 csr;
103 u8 res_14[0x20-0x14];
104 } hwncsr[3];
105 u8 res_60[0x80-0x60];
106 struct {
107 u32 gsr;
108 u8 res_84[0xa0-0x84];
109 } pllngsr[3];
110 u8 res_e0[0x100-0xe0];
111};
112
113struct ccsr_clk_ctrl {
114 struct {
115 u32 csr; /* core cluster n clock control status */
116 u8 res_04[0x20-0x04];
117 } clkcncsr[8];
118};
York Sun56cc3db2014-09-08 12:20:00 -0700[diff] [blame]119
120struct ccsr_reset {
121 u32 rstcr; /* 0x000 */
122 u32 rstcrsp; /* 0x004 */
123 u8 res_008[0x10-0x08]; /* 0x008 */
124 u32 rstrqmr1; /* 0x010 */
125 u32 rstrqmr2; /* 0x014 */
126 u32 rstrqsr1; /* 0x018 */
127 u32 rstrqsr2; /* 0x01c */
128 u32 rstrqwdtmrl; /* 0x020 */
129 u32 rstrqwdtmru; /* 0x024 */
130 u8 res_028[0x30-0x28]; /* 0x028 */
131 u32 rstrqwdtsrl; /* 0x030 */
132 u32 rstrqwdtsru; /* 0x034 */
133 u8 res_038[0x60-0x38]; /* 0x038 */
134 u32 brrl; /* 0x060 */
135 u32 brru; /* 0x064 */
136 u8 res_068[0x80-0x68]; /* 0x068 */
137 u32 pirset; /* 0x080 */
138 u32 pirclr; /* 0x084 */
139 u8 res_088[0x90-0x88]; /* 0x088 */
140 u32 brcorenbr; /* 0x090 */
141 u8 res_094[0x100-0x94]; /* 0x094 */
142 u32 rcw_reqr; /* 0x100 */
143 u32 rcw_completion; /* 0x104 */
144 u8 res_108[0x110-0x108]; /* 0x108 */
145 u32 pbi_reqr; /* 0x110 */
146 u32 pbi_completion; /* 0x114 */
147 u8 res_118[0xa00-0x118]; /* 0x118 */
148 u32 qmbm_warmrst; /* 0xa00 */
149 u32 soc_warmrst; /* 0xa04 */
150 u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
151 u32 ip_rev1; /* 0xbf8 */
152 u32 ip_rev2; /* 0xbfc */
153};
York Suna84cd722014-06-23 15:15:54 -0700[diff] [blame]154#endif /* __ARCH_FSL_LSCH3_IMMAP_H */