| Simon Glass | 8e44578 | 2019-05-07 21:41:16 -0600 | [diff] [blame] | 1 | if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL |
| Simon Glass | a0b0961 | 2016-03-16 07:44:43 -0600 | [diff] [blame] | 2 | |
| 3 | config SYS_BOARD |
| 4 | default "chromebook_samus" |
| 5 | |
| 6 | config SYS_VENDOR |
| 7 | default "google" |
| 8 | |
| 9 | config SYS_SOC |
| 10 | default "broadwell" |
| 11 | |
| 12 | config SYS_CONFIG_NAME |
| Simon Glass | 8e44578 | 2019-05-07 21:41:16 -0600 | [diff] [blame] | 13 | default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS |
| 14 | default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL |
| Simon Glass | a0b0961 | 2016-03-16 07:44:43 -0600 | [diff] [blame] | 15 | |
| Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 16 | config TEXT_BASE |
| Simon Glass | a0b0961 | 2016-03-16 07:44:43 -0600 | [diff] [blame] | 17 | default 0xffe00000 |
| 18 | |
| 19 | config BOARD_SPECIFIC_OPTIONS # dummy |
| 20 | def_bool y |
| 21 | select X86_RESET_VECTOR |
| Andy Shevchenko | 3e90244 | 2020-08-20 13:02:20 +0300 | [diff] [blame] | 22 | select USE_EARLY_BOARD_INIT |
| Simon Glass | a0b0961 | 2016-03-16 07:44:43 -0600 | [diff] [blame] | 23 | select INTEL_BROADWELL |
| 24 | select HAVE_INTEL_ME |
| 25 | select BOARD_ROMSIZE_KB_8192 |
| Bin Meng | 19ca463 | 2017-07-30 06:23:26 -0700 | [diff] [blame] | 26 | select SPI_FLASH_WINBOND |
| Simon Glass | a0b0961 | 2016-03-16 07:44:43 -0600 | [diff] [blame] | 27 | |
| 28 | config PCIE_ECAM_BASE |
| 29 | default 0xf0000000 |
| 30 | |
| 31 | config EARLY_POST_CROS_EC |
| 32 | bool "Enable early post to Chrome OS EC" |
| 33 | default y |
| 34 | |
| 35 | config SYS_CAR_ADDR |
| 36 | hex |
| 37 | default 0xff7c0000 |
| 38 | |
| 39 | config SYS_CAR_SIZE |
| 40 | hex |
| 41 | default 0x40000 |
| 42 | |
| 43 | endif |
| Simon Glass | 8e44578 | 2019-05-07 21:41:16 -0600 | [diff] [blame] | 44 | |
| 45 | if TARGET_CHROMEBOOK_SAMUS_TPL |
| 46 | |
| 47 | config BOARD_SPECIFIC_OPTIONS_TPL # dummy |
| 48 | def_bool y |
| 49 | select SPL |
| 50 | select TPL |
| 51 | |
| 52 | endif |