| Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <ppc_asm.tmpl> |
| 25 | #include <config.h> |
| 26 | #include <asm-ppc/mmu.h> |
| 27 | |
| 28 | /************************************************************************** |
| 29 | * TLB TABLE |
| 30 | * |
| 31 | * This table is used by the cpu boot code to setup the initial tlb |
| 32 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 33 | * this table lets each board set things up however they like. |
| 34 | * |
| 35 | * Pointer to the table is returned in r1 |
| 36 | * |
| 37 | *************************************************************************/ |
| 38 | .section .bootpg,"ax" |
| 39 | .globl tlbtab |
| 40 | |
| 41 | tlbtab: |
| 42 | tlbtab_start |
| 43 | |
| 44 | /* |
| 45 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to |
| 46 | * use the speed up boot process. It is patched after relocation to |
| 47 | * enable SA_I |
| 48 | */ |
| Stefan Roese | 0b86db7 | 2008-03-03 17:27:02 +0100 | [diff] [blame^] | 49 | #ifndef CONFIG_NAND_SPL |
| Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 50 | tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */ |
| Stefan Roese | 0b86db7 | 2008-03-03 17:27:02 +0100 | [diff] [blame^] | 51 | #else |
| 52 | tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G) |
| 53 | tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) |
| 54 | #endif |
| Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 55 | |
| 56 | /* |
| 57 | * TLB entries for SDRAM are not needed on this platform. |
| 58 | * They are dynamically generated in the SPD DDR(2) detection |
| 59 | * routine. |
| 60 | */ |
| 61 | |
| 62 | #ifdef CFG_INIT_RAM_DCACHE |
| 63 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
| 64 | tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) |
| 65 | #endif |
| 66 | |
| 67 | tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 68 | tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 69 | tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 70 | |
| 71 | tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 72 | tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 73 | tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 74 | tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
| 75 | |
| 76 | /* PCIe UTL register */ |
| 77 | tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I) |
| 78 | |
| 79 | /* TLB-entry for NAND */ |
| 80 | tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I) |
| 81 | |
| 82 | /* TLB-entry for CPLD */ |
| 83 | tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) |
| 84 | |
| 85 | /* TLB-entry for OCM */ |
| Stefan Roese | 0b86db7 | 2008-03-03 17:27:02 +0100 | [diff] [blame^] | 86 | tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) |
| Stefan Roese | 105350e | 2008-03-11 16:51:17 +0100 | [diff] [blame] | 87 | |
| 88 | /* TLB-entry for Local Configuration registers => peripherals */ |
| 89 | tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I) |
| 90 | |
| 91 | tlbtab_end |
| 92 | |
| 93 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
| 94 | /* |
| 95 | * For NAND booting the first TLB has to be reconfigured to full size |
| 96 | * and with caching disabled after running from RAM! |
| 97 | */ |
| 98 | #define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) |
| 99 | #define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) |
| 100 | #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) |
| 101 | |
| 102 | .globl reconfig_tlb0 |
| 103 | reconfig_tlb0: |
| 104 | sync |
| 105 | isync |
| 106 | addi r4,r0,0x0000 /* TLB entry #0 */ |
| 107 | lis r5,TLB00@h |
| 108 | ori r5,r5,TLB00@l |
| 109 | tlbwe r5,r4,0x0000 /* Save it out */ |
| 110 | lis r5,TLB01@h |
| 111 | ori r5,r5,TLB01@l |
| 112 | tlbwe r5,r4,0x0001 /* Save it out */ |
| 113 | lis r5,TLB02@h |
| 114 | ori r5,r5,TLB02@l |
| 115 | tlbwe r5,r4,0x0002 /* Save it out */ |
| 116 | sync |
| 117 | isync |
| 118 | blr |
| 119 | #endif |