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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Hideyuki Sano1da7a592012-06-27 10:35:35 +09002/*
3 * Configuation settings for the bonito board
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
Hideyuki Sano1da7a592012-06-27 10:35:35 +09006 */
7
8#ifndef __ARMADILLO_800EVA_H
9#define __ARMADILLO_800EVA_H
10
Hideyuki Sano1da7a592012-06-27 10:35:35 +090011#define CONFIG_SH_GPIO_PFC
12
13#include <asm/arch/rmobile.h>
14
Hideyuki Sano1da7a592012-06-27 10:35:35 +090015#define BOARD_LATE_INIT
16
Hideyuki Sano1da7a592012-06-27 10:35:35 +090017#define CONFIG_TMU_TIMER
Marek Vasut41316702018-08-24 21:52:53 +020018#define CONFIG_SYS_TIMER_COUNTS_DOWN
19#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
20#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
Hideyuki Sano1da7a592012-06-27 10:35:35 +090021
22/* STACK */
23#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
24#define STACK_AREA_SIZE 0xC000
25#define LOW_LEVEL_MERAM_STACK \
26 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
27
28/* MEMORY */
29#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000
30#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024)
31
Hideyuki Sano1da7a592012-06-27 10:35:35 +090032#define CONFIG_SYS_PBSIZE 256
Hideyuki Sano1da7a592012-06-27 10:35:35 +090033#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
34
35/* SCIF */
Hideyuki Sano1da7a592012-06-27 10:35:35 +090036#define CONFIG_CONS_SCIF1
37#define SCIF0_BASE 0xe6c40000
38#define SCIF1_BASE 0xe6c50000
39#define SCIF2_BASE 0xe6c60000
40#define SCIF4_BASE 0xe6c80000
41#define CONFIG_SCIF_A
Hideyuki Sano1da7a592012-06-27 10:35:35 +090042
43#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE)
44#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
45 504 * 1024 * 1024)
Hideyuki Sano1da7a592012-06-27 10:35:35 +090046#undef CONFIG_SYS_MEMTEST_SCRATCH
47#undef CONFIG_SYS_LOADS_BAUD_CHANGE
48
49#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)
50#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
51#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
52 64 * 1024 * 1024)
Hideyuki Sano1da7a592012-06-27 10:35:35 +090053
54#define CONFIG_SYS_MONITOR_BASE 0x00000000
55#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
Hideyuki Sano1da7a592012-06-27 10:35:35 +090057#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Hideyuki Sano1da7a592012-06-27 10:35:35 +090058
59/* FLASH */
Hideyuki Sano1da7a592012-06-27 10:35:35 +090060#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
61#define CONFIG_SYS_FLASH_BASE 0x00000000
62#define CONFIG_SYS_MAX_FLASH_SECT 512
63#define CONFIG_SYS_MAX_FLASH_BANKS 1
64#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
65
66#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
67#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
68#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
69#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
70
71/* ENV setting */
Hideyuki Sano1da7a592012-06-27 10:35:35 +090072#define CONFIG_ENV_OVERWRITE 1
Hideyuki Sano1da7a592012-06-27 10:35:35 +090073
74/* SH Ether */
Hideyuki Sano1da7a592012-06-27 10:35:35 +090075#define CONFIG_SH_ETHER_USE_PORT 0
76#define CONFIG_SH_ETHER_PHY_ADDR 0x0
77#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
78#define CONFIG_SH_ETHER_SH7734_MII (0x01)
79#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Hideyuki Sano1da7a592012-06-27 10:35:35 +090080#define CONFIG_BITBANGMII_MULTI
81
82/* Board Clock */
83#define CONFIG_SYS_CLK_FREQ 50000000
Nobuhiro Iwamatsu82e1ec72013-09-30 10:30:41 +090084#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Hideyuki Sano1da7a592012-06-27 10:35:35 +090085
86#endif /* __ARMADILLO_800EVA_H */