Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / ec5e3c2213923435de37e19a2cace7366654f468 / . / configs / am62x_evm_a53_defconfig
blob: 6c708dcb0521da6e1f45a6141140b41aca97f371 [file] [log] [blame]
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_K3=y
3CONFIG_SYS_MALLOC_F_LEN=0x8000
4CONFIG_SPL_LIBCOMMON_SUPPORT=y
5CONFIG_SPL_LIBGENERIC_SUPPORT=y
6CONFIG_NR_DRAM_BANKS=2
7CONFIG_SOC_K3_AM625=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]8CONFIG_TARGET_AM625_A53_EVM=y
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]9CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
Nikhil M Jaind0699df2023-04-10 14:19:10 +0530[diff] [blame]10CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]11CONFIG_SF_DEFAULT_SPEED=25000000
Sjoerd Simons05b61862022-12-20 16:21:44 +0100[diff] [blame]12CONFIG_SPL_DM_SPI=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]13CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk"
14CONFIG_SPL_TEXT_BASE=0x80080000
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]15CONFIG_OF_LIBFDT_OVERLAY=y
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]16CONFIG_DM_RESET=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]17CONFIG_SPL_MMC=y
18CONFIG_SPL_SERIAL=y
19CONFIG_SPL_STACK_R_ADDR=0x82000000
Jonathan Humphreys0ad2e9d2024-04-08 16:10:56 -0500[diff] [blame]20CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
21CONFIG_SPL_BSS_START_ADDR=0x80c80000
22CONFIG_SPL_BSS_MAX_SIZE=0x80000
23CONFIG_SPL_STACK_R=y
Nikhil M Jaind0699df2023-04-10 14:19:10 +0530[diff] [blame]24CONFIG_SPL_SIZE_LIMIT=0x40000
25CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]26CONFIG_SPL_FS_FAT=y
27CONFIG_SPL_LIBDISK_SUPPORT=y
Sjoerd Simons05b61862022-12-20 16:21:44 +0100[diff] [blame]28CONFIG_SPL_SPI_FLASH_SUPPORT=y
Dhruva Golec52e8d32022-10-27 20:23:11 +0530[diff] [blame]29CONFIG_SPL_SPI=y
Jan Kiszka262b6902023-08-25 13:03:01 -0500[diff] [blame]30# CONFIG_PSCI_RESET is not set
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]31# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
32CONFIG_SPL_LOAD_FIT=y
33CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
Nishanth Menon4b2a1412023-08-25 13:02:52 -0500[diff] [blame]34CONFIG_BOOTSTD_FULL=y
Tom Rini914a8c02024-01-03 09:26:16 -0500[diff] [blame]35CONFIG_SYS_BOOTM_LEN=0x800000
Martyn Welch322e4732024-03-26 14:26:33 +0000[diff] [blame]36CONFIG_BOOTCOMMAND="run findfdt; run envboot; bootflow scan -lb"
Nishanth Menon6850daf2024-02-12 13:47:19 -0600[diff] [blame]37CONFIG_BOARD_LATE_INIT=y
Manorit Chawdhryc0d1bf82023-07-25 13:09:18 +0530[diff] [blame]38CONFIG_SPL_MAX_SIZE=0x58000
Nikhil M Jaind0699df2023-04-10 14:19:10 +0530[diff] [blame]39CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]40CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]41CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
42CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
43CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
44CONFIG_SPL_DM_MAILBOX=y
Dhruva Golec52e8d32022-10-27 20:23:11 +0530[diff] [blame]45CONFIG_SPL_DM_SPI_FLASH=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]46CONFIG_SPL_POWER_DOMAIN=y
Dhruva Golec52e8d32022-10-27 20:23:11 +0530[diff] [blame]47# CONFIG_SPL_SPI_FLASH_TINY is not set
48CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
Dhruva Golec52e8d32022-10-27 20:23:11 +0530[diff] [blame]49CONFIG_SPL_SPI_LOAD=y
50CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]51CONFIG_SPL_YMODEM_SUPPORT=y
Jonathan Humphreys3559a612024-04-08 16:10:57 -0500[diff] [blame]52CONFIG_CMD_BOOTEFI_SELFTEST=y
53CONFIG_CMD_NVEDIT_EFI=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]54CONFIG_CMD_MMC=y
Jonathan Humphreys3559a612024-04-08 16:10:57 -0500[diff] [blame]55CONFIG_CMD_EFIDEBUG=y
Tom Rinib9dc6842024-04-22 17:24:09 -0600[diff] [blame]56CONFIG_MMC_SPEED_MODE_SET=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]57CONFIG_OF_CONTROL=y
58CONFIG_SPL_OF_CONTROL=y
59CONFIG_MULTI_DTB_FIT=y
60CONFIG_SPL_MULTI_DTB_FIT=y
61CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
62CONFIG_NET_RANDOM_ETHADDR=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]63CONFIG_SPL_DM=y
64CONFIG_SPL_DM_SEQ_ALIAS=y
65CONFIG_REGMAP=y
66CONFIG_SPL_REGMAP=y
67CONFIG_SPL_OF_TRANSLATE=y
68CONFIG_CLK=y
69CONFIG_SPL_CLK=y
70CONFIG_CLK_TI_SCI=y
Sjoerd Simonse3a4b372022-12-20 16:21:46 +0100[diff] [blame]71CONFIG_DMA_CHANNELS=y
72CONFIG_TI_K3_NAVSS_UDMA=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]73CONFIG_TI_SCI_PROTOCOL=y
74CONFIG_DM_MAILBOX=y
75CONFIG_K3_SEC_PROXY=y
Nishanth Menoncb897512023-08-25 13:02:59 -0500[diff] [blame]76CONFIG_SUPPORT_EMMC_BOOT=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]77CONFIG_MMC_SDHCI=y
78CONFIG_MMC_SDHCI_ADMA=y
79CONFIG_SPL_MMC_SDHCI_ADMA=y
80CONFIG_MMC_SDHCI_AM654=y
Tom Riniddb1ec12024-01-10 13:46:10 -0500[diff] [blame]81CONFIG_MTD=y
Dhruva Golec52e8d32022-10-27 20:23:11 +0530[diff] [blame]82CONFIG_DM_SPI_FLASH=y
Dhruva Golec52e8d32022-10-27 20:23:11 +0530[diff] [blame]83CONFIG_SPI_FLASH_SFDP_SUPPORT=y
84CONFIG_SPI_FLASH_SOFT_RESET=y
85CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
86CONFIG_SPI_FLASH_SPANSION=y
Sjoerd Simonse6cc0412022-12-20 16:21:43 +0100[diff] [blame]87CONFIG_SPI_FLASH_S28HX_T=y
Sjoerd Simonse3a4b372022-12-20 16:21:46 +0100[diff] [blame]88CONFIG_PHY_TI_DP83867=y
89CONFIG_PHY_FIXED=y
90CONFIG_TI_AM65_CPSW_NUSS=y
91CONFIG_PHY=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]92CONFIG_PINCTRL=y
93CONFIG_SPL_PINCTRL=y
94CONFIG_PINCTRL_SINGLE=y
95CONFIG_POWER_DOMAIN=y
96CONFIG_TI_SCI_POWER_DOMAIN=y
97CONFIG_K3_SYSTEM_CONTROLLER=y
98CONFIG_REMOTEPROC_TI_K3_ARM64=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]99CONFIG_RESET_TI_SCI=y
Jonathan Humphreys4f23b542024-04-08 16:10:58 -0500[diff] [blame]100CONFIG_DM_RTC=y
101CONFIG_RTC_EMULATION=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]102CONFIG_DM_SERIAL=y
103CONFIG_SOC_DEVICE=y
104CONFIG_SOC_DEVICE_TI_K3=y
105CONFIG_SOC_TI=y
Dhruva Golec52e8d32022-10-27 20:23:11 +0530[diff] [blame]106CONFIG_SPI=y
107CONFIG_DM_SPI=y
108CONFIG_CADENCE_QSPI=y
Vignesh Raghavendrabf9bca72022-05-25 13:38:49 +0530[diff] [blame]109CONFIG_SYSRESET=y
110CONFIG_SPL_SYSRESET=y
111CONFIG_SYSRESET_TI_SCI=y
112CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
Jonathan Humphreys4f23b542024-04-08 16:10:58 -0500[diff] [blame]113CONFIG_EFI_SET_TIME=y