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git01.mediatek.com / filogic / uboot / 0b517738798e305c33dd5a40e54d34787287c936 / . / configs / chromebook_jerry_defconfig
blob: f6056f85ccfaa1ce5f416712153d1835e4f3dc56 [file] [log] [blame]
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x00100000
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]4CONFIG_ROCKCHIP_RK3288=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]5# CONFIG_SPL_MMC_SUPPORT is not set
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]6CONFIG_TARGET_CHROMEBOOK_JERRY=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=1
8CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]9CONFIG_DEBUG_UART_BASE=0xff690000
10CONFIG_DEBUG_UART_CLOCK=24000000
Simon Glass219d6122016-09-12 23:18:57 -0600[diff] [blame]11CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassb24fdca2016-09-12 23:18:58 -0600[diff] [blame]12CONFIG_SPL_SPI_SUPPORT=y
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]13CONFIG_DEBUG_UART=y
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]14# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]15CONFIG_SILENT_CONSOLE=y
Simon Glassb7e0e852018-12-27 20:15:23 -0700[diff] [blame]16CONFIG_LOG=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]17CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]18# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]19CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Glasse608ced2017-05-31 17:57:33 -0600[diff] [blame]20CONFIG_BOARD_EARLY_INIT_F=y
Simon Goldschmidtcc4078c2018-09-30 14:31:53 +0200[diff] [blame]21CONFIG_SPL_TEXT_BASE=0xff704000
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]22CONFIG_SPL_STACK_R=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]23CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]24CONFIG_SPL_SPI_LOAD=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]25CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]26CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]27CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]28CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]29CONFIG_CMD_SF=y
Simon Glass86b1b652017-08-04 16:34:46 -0600[diff] [blame]30CONFIG_CMD_SF_TEST=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]31CONFIG_CMD_SPI=y
Eddie Caib3501fe2017-12-15 08:17:13 +0800[diff] [blame]32CONFIG_CMD_USB=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]33# CONFIG_CMD_SETEXPR is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]34CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]35CONFIG_CMD_TIME=y
Simon Glassb7e0e852018-12-27 20:15:23 -0700[diff] [blame]36CONFIG_CMD_SOUND=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]37CONFIG_CMD_PMIC=y
38CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]39# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]40# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]41CONFIG_SPL_PARTITION_UUIDS=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]42CONFIG_SPL_OF_CONTROL=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]43CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
Simon Glass95994612016-11-13 14:22:09 -0700[diff] [blame]44CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]45CONFIG_REGMAP=y
huang lindd8515e2015-11-17 14:20:13 +0800[diff] [blame]46CONFIG_SPL_REGMAP=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]47CONFIG_SYSCON=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]48CONFIG_SPL_SYSCON=y
Simon Glass70bad912016-01-21 19:43:49 -0700[diff] [blame]49# CONFIG_SPL_SIMPLE_BUS is not set
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]50CONFIG_CLK=y
51CONFIG_SPL_CLK=y
Alex Kiernane80d2942018-05-29 15:30:55 +0000[diff] [blame]52CONFIG_FASTBOOT_FLASH=y
53CONFIG_FASTBOOT_FLASH_MMC_DEV=0
54CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]55CONFIG_ROCKCHIP_GPIO=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]56CONFIG_I2C_CROS_EC_TUNNEL=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]57CONFIG_SYS_I2C_ROCKCHIP=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]58CONFIG_I2C_MUX=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]59CONFIG_DM_KEYBOARD=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]60CONFIG_CROS_EC_KEYB=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]61CONFIG_CROS_EC=y
62CONFIG_CROS_EC_SPI=y
Simon Glassaf0b7442016-01-21 19:43:36 -0700[diff] [blame]63CONFIG_PWRSEQ=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]64CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]65CONFIG_MMC_DW_ROCKCHIP=y
Vignesh Re57ea112019-02-05 11:29:10 +0530[diff] [blame]66CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]67CONFIG_SF_DEFAULT_SPEED=20000000
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]68CONFIG_PINCTRL=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]69CONFIG_SPL_PINCTRL=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]70CONFIG_DM_PMIC=y
Simon Glasscf88b7c2016-01-21 19:44:13 -0700[diff] [blame]71# CONFIG_SPL_PMIC_CHILDREN is not set
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]72CONFIG_PMIC_RK8XX=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]73CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]74CONFIG_REGULATOR_RK8XX=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]75CONFIG_PWM_ROCKCHIP=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]76CONFIG_RAM=y
77CONFIG_SPL_RAM=y
Bin Meng63c10982015-09-28 05:14:15 -0700[diff] [blame]78CONFIG_DEBUG_UART_SHIFT=2
Simon Glassb7e0e852018-12-27 20:15:23 -0700[diff] [blame]79CONFIG_SOUND=y
80CONFIG_I2S=y
81CONFIG_I2S_ROCKCHIP=y
Simon Glass3b4057b2016-01-21 19:43:35 -0700[diff] [blame]82CONFIG_ROCKCHIP_SPI=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]83CONFIG_SYSRESET=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]84CONFIG_USB=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]85CONFIG_ROCKCHIP_USB2_PHY=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]86CONFIG_USB_GADGET=y
Maxime Ripard7f78b9d2017-09-07 08:58:08 +0200[diff] [blame]87CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
88CONFIG_USB_GADGET_VENDOR_NUM=0x2207
89CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]90CONFIG_USB_GADGET_DWC2_OTG=y
Lukasz Majewskie364e4b2018-01-29 19:25:54 +0100[diff] [blame]91CONFIG_USB_FUNCTION_MASS_STORAGE=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]92CONFIG_DM_VIDEO=y
Simon Glassd56d6eb2018-12-27 15:25:19 -0700[diff] [blame]93CONFIG_CONSOLE_TRUETYPE=y
Anatolij Gustschin4601eb42016-01-25 17:17:22 +0100[diff] [blame]94CONFIG_DISPLAY=y
Simon Glassabd2c152016-01-21 19:45:19 -0700[diff] [blame]95CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com735ddea2017-04-17 22:24:23 +0800[diff] [blame]96CONFIG_DISPLAY_ROCKCHIP_EDP=y
97CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Simon Glassd56d6eb2018-12-27 15:25:19 -0700[diff] [blame]98# CONFIG_USE_PRIVATE_LIBGCC is not set
Simon Glass2ac46482015-12-29 05:22:45 -0700[diff] [blame]99CONFIG_USE_TINY_PRINTF=y
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600[diff] [blame]100CONFIG_CMD_DHRYSTONE=y
101CONFIG_ERRNO_STR=y